| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | SIGenRegisterInfo.pl | 248 my ($reg_width, $sub_reg_ref, @types) = @_;
249 return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
253 my ($reg_width, $sub_reg_ref, @types) = @_;
254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
258 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
260 my $component_count = $reg_width / 32;
263 my $reg_name = $reg_prefix . $i . '_' . $reg_width;
269 …print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>…
274 if ($class_prefix eq 'SReg' and $reg_width == 64) {
279 if ($class_prefix eq 'SReg' and $reg_width == 64) {
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_fs_reg_allocate.cpp | 34 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width) in assign_reg() argument
38 reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width; in assign_reg()
48 int reg_width = c->dispatch_width / 8; in assign_regs_trivial() local
51 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width); in assign_regs_trivial()
54 this->virtual_grf_sizes[i - 1] * reg_width); in assign_regs_trivial()
61 assign_reg(hw_reg_mapping, &inst->dst, reg_width); in assign_regs_trivial()
62 assign_reg(hw_reg_mapping, &inst->src[0], reg_width); in assign_regs_trivial()
63 assign_reg(hw_reg_mapping, &inst->src[1], reg_width); in assign_regs_trivial()
64 assign_reg(hw_reg_mapping, &inst->src[2], reg_width); in assign_regs_trivial()
78 int reg_width, in brw_alloc_reg_set_for_classes() argument
[all …]
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| D | brw_fs_visitor.cpp | 924 int reg_width = c->dispatch_width / 8; in emit_texture_gen5() local
938 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type), in emit_texture_gen5()
955 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type), in emit_texture_gen5()
960 mlen += vector_elements * reg_width; in emit_texture_gen5()
963 mlen = MAX2(mlen, header_present + 4 * reg_width); in emit_texture_gen5()
966 mlen += reg_width; in emit_texture_gen5()
975 mlen = MAX2(mlen, header_present + 4 * reg_width); in emit_texture_gen5()
977 mlen += reg_width; in emit_texture_gen5()
982 mlen = MAX2(mlen, header_present + 4 * reg_width); in emit_texture_gen5()
984 mlen += reg_width; in emit_texture_gen5()
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_blit.c | 260 float reg_width, float reg_height, in calc_tex_coords() argument
264 buf[1] = buf[0] + reg_width / img_width; in calc_tex_coords()
278 unsigned reg_width, unsigned reg_height, in emit_draw_packet() argument
287 reg_width, reg_height, in emit_draw_packet()
295 verts[4] = dst_x_offset + reg_width; in emit_draw_packet()
300 verts[8] = dst_x_offset + reg_width; in emit_draw_packet()
358 unsigned reg_width, in r100_blit() argument
375 if (reg_width + src_x_offset > src_width) in r100_blit()
376 reg_width = src_width - src_x_offset; in r100_blit()
379 if (reg_width + dst_x_offset > dst_width) in r100_blit()
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| D | radeon_common_context.h | 495 unsigned reg_width,
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 385 float reg_width, float reg_height, in calc_tex_coords() argument
389 buf[1] = buf[0] + reg_width / img_width; in calc_tex_coords()
403 unsigned reg_width, unsigned reg_height, in emit_draw_packet() argument
412 reg_width, reg_height, in emit_draw_packet()
420 verts[4] = dst_x_offset + reg_width; in emit_draw_packet()
425 verts[8] = dst_x_offset + reg_width; in emit_draw_packet()
480 unsigned reg_width, in r200_blit() argument
497 if (reg_width + src_x_offset > src_width) in r200_blit()
498 reg_width = src_width - src_x_offset; in r200_blit()
501 if (reg_width + dst_x_offset > dst_width) in r200_blit()
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| D | radeon_common_context.h | 495 unsigned reg_width,
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1317 int64_t Rotate(unsigned reg_width,
1321 int64_t ExtendValue(unsigned reg_width,
|