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Searched refs:res13 (Results 1 – 12 of 12) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c333 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
433 ILVR_B2_SH(zero, dst12, zero, dst13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
434 ADD2(res12, out12, res13, out13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
435 CLIP_SH2_0_255(res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
436 PCKEV_B2_SH(res12, res12, res13, res13, res12, res13); in vpx_iadst16_1d_columns_addblk_msa()
438 ST8x1_UB(res13, dst + 13 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.resinfo.ll35 %res13 = call <4 x i32> @llvm.SI.resinfo(i32 %a13, <32 x i8> undef, i32 13)
71 %t20 = extractelement <4 x i32> %res13, i32 0
72 %t21 = extractelement <4 x i32> %res13, i32 2
73 %t22 = extractelement <4 x i32> %res13, i32 3
Dllvm.SI.sampled.ll62 %res13 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v13,
102 %t20 = extractelement <4 x float> %res13, i32 0
103 %t21 = extractelement <4 x float> %res13, i32 2
104 %t22 = extractelement <4 x float> %res13, i32 3
Dllvm.SI.sample.ll62 %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13,
102 %t20 = extractelement <4 x float> %res13, i32 0
103 %t21 = extractelement <4 x float> %res13, i32 2
104 %t22 = extractelement <4 x float> %res13, i32 3
Dllvm.AMDGPU.tex.ll34 %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res12, i32 0, i32 0, i32 13)
35 %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14)
Dfetch-limits.r700+.ll51 %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 0, i32 0, i32 1)
61 %g = fadd <4 x float> %res12, %res13
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll66 ; CHECK-NEXT: %res13 = load i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.l…
67 %res13 = load i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
122 ; CHECK-NEXT: %res13 = load atomic volatile i8, i8* %ptr1 singlethread unordered, align 1
123 %res13 = load atomic volatile i8, i8* %ptr1 singlethread unordered, align 1
279 ; CHECK-NEXT: %res13 = extractvalue { i32, i1 } [[TMP]], 0
280 %res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
DmiscInstructions.3.2.ll153 ; CHECK-NEXT: %res13 = fcmp une float %x1, %x2
154 %res13 = fcmp une float %x1, %x2
/external/clang/test/SemaCXX/
Daltivec.cpp32 int res13[vec_step(*pvi) == 4 ? 1 : -1]; in test_vec_step() local
/external/clang/test/SemaOpenCL/
Dvec_step.cl29 …int res13 = vec_step(*incomplete1); // expected-error {{'vec_step' requires built-in scalar or vec…
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h630 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
993 res13 = mult_round_shift(&t2, &t3, &k__cospi_p06_p26, in FDCT16x16_2D()
1000 overflow = check_epi16_overflow_x4(&res05, &res13, &res11, &res03); in FDCT16x16_2D()
1013 &res12, &res13, &res14, &res15, in FDCT16x16_2D()
/external/llvm/test/CodeGen/X86/
Davx512-intrinsics.ll5592 %res13 = or i8 %res11, %res12
5593 ret i8 %res13
5636 %res13 = and i8 %res11, %res12
5637 ret i8 %res13
5766 %res13 = fadd <2 x double> %res11, %res12
5767 ret <2 x double> %res13
5791 %res13 = fadd <4 x float> %res11, %res12
5792 ret <4 x float> %res13