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Searched refs:res14 (Results 1 – 10 of 10) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c333 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
481 ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
482 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
483 CLIP_SH2_0_255(res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
484 PCKEV_B2_SH(res14, res14, res15, res15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
485 ST8x1_UB(res14, dst + 5 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.SI.resinfo.ll36 %res14 = call <4 x i32> @llvm.SI.resinfo(i32 %a14, <32 x i8> undef, i32 14)
76 %t24 = extractelement <4 x i32> %res14, i32 1
77 %t25 = extractelement <4 x i32> %res14, i32 2
78 %t26 = extractelement <4 x i32> %res14, i32 3
Dllvm.SI.sampled.ll64 %res14 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14,
107 %t24 = extractelement <4 x float> %res14, i32 1
108 %t25 = extractelement <4 x float> %res14, i32 2
109 %t26 = extractelement <4 x float> %res14, i32 3
Dllvm.SI.sample.ll64 %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
107 %t24 = extractelement <4 x float> %res14, i32 1
108 %t25 = extractelement <4 x float> %res14, i32 2
109 %t26 = extractelement <4 x float> %res14, i32 3
Dllvm.AMDGPU.tex.ll35 %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14)
36 %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res14, i32 0, i32 0, i32 15)
Dfetch-limits.r700+.ll52 %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1)
62 %h = fadd <4 x float> %res14, %res15
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll69 ; CHECK-NEXT: %res14 = load volatile i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
70 %res14 = load volatile i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
125 ; CHECK-NEXT: %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
126 %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
283 ; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
284 %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
DmiscInstructions.3.2.ll156 ; CHECK-NEXT: %res14 = fcmp uno float %x1, %x2
157 %res14 = fcmp uno float %x1, %x2
/external/clang/test/SemaOpenCL/
Dvec_step.cl30 …int res14 = vec_step(int16*); // expected-error {{'vec_step' requires built-in scalar or vector ty…
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h630 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
856 res14 = mult_round_shift(&t0, &t1, &k__cospi_m04_p28, in FDCT16x16_2D()
863 overflow = check_epi16_overflow_x4(&res02, &res14, in FDCT16x16_2D()
1013 &res12, &res13, &res14, &res15, in FDCT16x16_2D()