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Searched refs:rmesa (Results 1 – 25 of 56) sorted by relevance

123

/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c55 void r200SetUpAtomList( r200ContextPtr rmesa ) in r200SetUpAtomList() argument
59 mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; in r200SetUpAtomList()
61 make_empty_list(&rmesa->radeon.hw.atomlist); in r200SetUpAtomList()
62 rmesa->radeon.hw.atomlist.name = "atom-list"; in r200SetUpAtomList()
64 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); in r200SetUpAtomList()
65 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); in r200SetUpAtomList()
66 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); in r200SetUpAtomList()
67 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); in r200SetUpAtomList()
68 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); in r200SetUpAtomList()
69 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); in r200SetUpAtomList()
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Dr200_state_init.c166 static int cmdpkt( r200ContextPtr rmesa, int id ) in cmdpkt() argument
224 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
225 (void) rmesa; \
232 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
233 …return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (…
239 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
240 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
246 r200ContextPtr rmesa = R200_CONTEXT(ctx); \
248 …return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (A…
257 …CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), …
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Dr200_state.c69 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200AlphaFunc() local
70 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in r200AlphaFunc()
75 R200_STATECHANGE( rmesa, ctx ); in r200AlphaFunc()
107 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in r200AlphaFunc()
113 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200BlendColor() local
114 R200_STATECHANGE( rmesa, ctx ); in r200BlendColor()
119 …rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3… in r200BlendColor()
204 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200_set_blend_state() local
205 GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & in r200_set_blend_state()
215 R200_STATECHANGE( rmesa, ctx ); in r200_set_blend_state()
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Dradeon_dma.c140 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vector() local
144 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); in rcommon_emit_vector()
148 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vector()
175 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vecfog() local
182 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); in rcommon_emit_vecfog()
186 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vecfog()
204 void radeon_init_dma(radeonContextPtr rmesa) in radeon_init_dma() argument
206 make_empty_list(&rmesa->dma.free); in radeon_init_dma()
207 make_empty_list(&rmesa->dma.wait); in radeon_init_dma()
208 make_empty_list(&rmesa->dma.reserved); in radeon_init_dma()
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Dr200_tcl.c105 #define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx)
124 R200_STATECHANGE( rmesa, lin ); \
125 radeonEmitState(&rmesa->radeon); \
129 R200_STATECHANGE( rmesa, lin ); \
131 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
134 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
136 radeonEmitState(&rmesa->radeon); \
140 #define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr )
142 static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) in r200AllocElts() argument
144 if (rmesa->radeon.dma.flush == r200FlushElts && in r200AllocElts()
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Dr200_swtcl.c64 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
65 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
66 rmesa->radeon.swtcl.vertex_attr_count++; \
72 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
75 rmesa->radeon.swtcl.vertex_attr_count++; \
80 r200ContextPtr rmesa = R200_CONTEXT( ctx ); in r200SetVertexFormat() local
98 rmesa->radeon.swtcl.vertex_attr_count = 0; in r200SetVertexFormat()
103 if ( !rmesa->swtcl.needproj || in r200SetVertexFormat()
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Dr200_context.c74 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200GetString() local
77 GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : in r200GetString()
78 rmesa->radeon.radeonScreen->AGPMode; in r200GetString()
88 !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) in r200GetString()
148 r200ContextPtr rmesa = (r200ContextPtr)radeon; in r200_get_lock() local
151 R200_STATECHANGE( rmesa, ctx ); in r200_get_lock()
152 if (rmesa->radeon.sarea->tiling_enabled) { in r200_get_lock()
153 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; in r200_get_lock()
155 else rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= ~R200_COLOR_TILE_ENABLE; in r200_get_lock()
157 if ( sarea->ctx_owner != rmesa->radeon.dri.hwContext ) { in r200_get_lock()
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Dr200_ioctl.h48 extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count);
49 extern void r200EmitVertexAOS( r200ContextPtr rmesa,
54 extern void r200EmitVbufPrim( r200ContextPtr rmesa,
60 extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa,
64 extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset);
68 void r200SetUpAtomList( r200ContextPtr rmesa );
76 #define R200_NEWPRIM( rmesa ) \ argument
78 if ( rmesa->radeon.dma.flush ) \
79 rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
85 #define R200_STATECHANGE( rmesa, ATOM ) \ argument
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Dr200_texstate.c305 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateTextureEnv() local
308 GLuint color_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] & in r200UpdateTextureEnv()
311 GLuint alpha_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] & in r200UpdateTextureEnv()
332 color_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXC_OUTPUT_REG_SHIFT) | in r200UpdateTextureEnv()
335 alpha_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXA_OUTPUT_REG_SHIFT) | in r200UpdateTextureEnv()
403 [rmesa->state.texture.unit[replaceargs - 1].outputreg]; in r200UpdateTextureEnv()
428 [rmesa->state.texture.unit[unit - 1].outputreg]; in r200UpdateTextureEnv()
485 [rmesa->state.texture.unit[replaceargs - 1].outputreg]; in r200UpdateTextureEnv()
510 [rmesa->state.texture.unit[unit - 1].outputreg]; in r200UpdateTextureEnv()
714 if ( rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] != color_combine || in r200UpdateTextureEnv()
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Dradeon_common.c109 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in radeonUpdateScissor() local
134 rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); in radeonUpdateScissor()
135 rmesa->state.scissor.rect.y1 = CLAMP(y1, min_y, max_y); in radeonUpdateScissor()
136 rmesa->state.scissor.rect.x2 = CLAMP(x2, min_x, max_x); in radeonUpdateScissor()
137 rmesa->state.scissor.rect.y2 = CLAMP(y2, min_y, max_y); in radeonUpdateScissor()
139 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
140 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
385 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); in radeonReadBuffer() local
386 const GLboolean was_front_buffer_reading = rmesa->is_front_buffer_reading; in radeonReadBuffer()
387 rmesa->is_front_buffer_reading = (mode == GL_FRONT_LEFT) in radeonReadBuffer()
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Dr200_fragshader.c126 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateFSArith() local
131 R200_STATECHANGE( rmesa, afs[0] ); in r200UpdateFSArith()
132 R200_STATECHANGE( rmesa, afs[1] ); in r200UpdateFSArith()
135 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
138 afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; in r200UpdateFSArith()
320 afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; in r200UpdateFSArith()
322 rmesa->afs_loaded = ctx->ATIFragmentShader.Current; in r200UpdateFSArith()
326 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200UpdateFSRouting() local
330 R200_STATECHANGE( rmesa, ctx ); in r200UpdateFSRouting()
331 R200_STATECHANGE( rmesa, cst ); in r200UpdateFSRouting()
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Dr200_tex.c301 r200ContextPtr rmesa = R200_CONTEXT(ctx); in r200TexEnv() local
318 if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) { in r200TexEnv()
319 R200_STATECHANGE( rmesa, tf ); in r200TexEnv()
320 rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor; in r200TexEnv()
336 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? in r200TexEnv()
342 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) { in r200TexEnv()
343 R200_STATECHANGE( rmesa, tex[unit] ); in r200TexEnv()
344 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK; in r200TexEnv()
345 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b; in r200TexEnv()
351 R200_STATECHANGE( rmesa, spr ); in r200TexEnv()
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/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c65 void radeonSetUpAtomList( r100ContextPtr rmesa ) in radeonSetUpAtomList() argument
67 int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; in radeonSetUpAtomList()
69 make_empty_list(&rmesa->radeon.hw.atomlist); in radeonSetUpAtomList()
70 rmesa->radeon.hw.atomlist.name = "atom-list"; in radeonSetUpAtomList()
72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); in radeonSetUpAtomList()
73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); in radeonSetUpAtomList()
74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); in radeonSetUpAtomList()
75 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); in radeonSetUpAtomList()
76 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); in radeonSetUpAtomList()
77 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); in radeonSetUpAtomList()
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Dradeon_state.c68 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonAlphaFunc() local
69 int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; in radeonAlphaFunc()
74 RADEON_STATECHANGE( rmesa, ctx ); in radeonAlphaFunc()
106 rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; in radeonAlphaFunc()
112 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonBlendEquationSeparate() local
113 GLuint b = rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] & ~RADEON_COMB_FCN_MASK; in radeonBlendEquationSeparate()
136 FALLBACK( rmesa, RADEON_FALLBACK_BLEND_EQ, fallback ); in radeonBlendEquationSeparate()
138 RADEON_STATECHANGE( rmesa, ctx ); in radeonBlendEquationSeparate()
139 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = b; in radeonBlendEquationSeparate()
142 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_ROP_ENABLE; in radeonBlendEquationSeparate()
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Dradeon_dma.c140 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vector() local
144 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * 4, 32); in rcommon_emit_vector()
148 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vector()
175 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in rcommon_emit_vecfog() local
182 radeonAllocDmaRegion( rmesa, &aos->bo, &aos->offset, size * 4, 32 ); in rcommon_emit_vecfog()
186 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, size * count * 4, 32); in rcommon_emit_vecfog()
204 void radeon_init_dma(radeonContextPtr rmesa) in radeon_init_dma() argument
206 make_empty_list(&rmesa->dma.free); in radeon_init_dma()
207 make_empty_list(&rmesa->dma.wait); in radeon_init_dma()
208 make_empty_list(&rmesa->dma.reserved); in radeon_init_dma()
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Dradeon_tcl.c108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
114 #define GET_MESA_ELTS() rmesa->tcl.Elts
128 RADEON_STATECHANGE( rmesa, lin ); \
129 radeonEmitState(&rmesa->radeon); \
133 RADEON_STATECHANGE( rmesa, lin ); \
135 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
138 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
140 radeonEmitState(&rmesa->radeon); \
145 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
147 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr ) in radeonAllocElts() argument
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Dradeon_swtcl.c69 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
70 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
71 rmesa->radeon.swtcl.vertex_attr_count++; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
78 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
79 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
80 rmesa->radeon.swtcl.vertex_attr_count++; \
92 r100ContextPtr rmesa = R100_CONTEXT( ctx ); in radeonSetVertexFormat() local
109 rmesa->radeon.swtcl.vertex_attr_count = 0; in radeonSetVertexFormat()
114 if ( !rmesa->swtcl.needproj || in radeonSetVertexFormat()
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Dradeon_state_init.c161 static int cmdpkt( r100ContextPtr rmesa, int id ) in cmdpkt() argument
197 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
198 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
504 void radeonInitState( r100ContextPtr rmesa ) in radeonInitState() argument
506 struct gl_context *ctx = rmesa->radeon.glCtx; in radeonInitState()
509 rmesa->radeon.Fallback = 0; in radeonInitState()
512 rmesa->radeon.hw.max_state_size = 0; in radeonInitState()
516 rmesa->hw.ATOM.cmd_size = SZ; \ in radeonInitState()
517 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in radeonInitState()
518 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ in radeonInitState()
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Dradeon_context.c96 r100ContextPtr rmesa = (r100ContextPtr)radeon; in r100_get_lock() local
99 RADEON_STATECHANGE(rmesa, ctx); in r100_get_lock()
100 if (rmesa->radeon.sarea->tiling_enabled) { in r100_get_lock()
101 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= in r100_get_lock()
104 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= in r100_get_lock()
108 if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { in r100_get_lock()
109 sarea->ctx_owner = rmesa->radeon.dri.hwContext; in r100_get_lock()
113 static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) in r100_vtbl_emit_cs_header() argument
119 r100ContextPtr rmesa = (r100ContextPtr)radeon; in r100_vtbl_pre_emit_state() local
122 rmesa->hw.zbs.dirty = 1; in r100_vtbl_pre_emit_state()
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Dradeon_ioctl.h43 extern void radeonEmitVertexAOS( r100ContextPtr rmesa,
48 extern void radeonEmitVbufPrim( r100ContextPtr rmesa,
56 extern GLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa,
62 extern void radeonEmitAOS( r100ContextPtr rmesa,
66 extern void radeonEmitBlit( r100ContextPtr rmesa,
76 extern void radeonEmitWait( r100ContextPtr rmesa, GLuint flags );
78 extern void radeonFlushCmdBuf( r100ContextPtr rmesa, const char * );
83 extern void radeonGetAllParams( r100ContextPtr rmesa );
84 extern void radeonSetUpAtomList( r100ContextPtr rmesa );
92 #define RADEON_NEWPRIM( rmesa ) \ argument
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Dradeon_texstate.c265 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonUpdateTextureEnv() local
295 rmesa->state.texture.unit[unit].format = 0; in radeonUpdateTextureEnv()
296 rmesa->state.texture.unit[unit].envMode = 0; in radeonUpdateTextureEnv()
595 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine || in radeonUpdateTextureEnv()
596 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) { in radeonUpdateTextureEnv()
597 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonUpdateTextureEnv()
598 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine; in radeonUpdateTextureEnv()
599 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine; in radeonUpdateTextureEnv()
740 static void disable_tex_obj_state( r100ContextPtr rmesa, in disable_tex_obj_state() argument
743 RADEON_STATECHANGE( rmesa, tex[unit] ); in disable_tex_obj_state()
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Dradeon_maos_arrays.c86 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in emit_tex_vector() local
101 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * 4, 32); in emit_tex_vector()
106 radeonAllocDmaRegion(rmesa, &aos->bo, &aos->offset, emitsize * count * 4, 32); in emit_tex_vector()
146 r100ContextPtr rmesa = R100_CONTEXT( ctx ); in radeonEmitArrays() local
159 if (!rmesa->tcl.obj.buf) in radeonEmitArrays()
161 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
179 if (!rmesa->tcl.norm.buf) in radeonEmitArrays()
181 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
205 if (!rmesa->tcl.rgba.buf) in radeonEmitArrays()
207 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
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Dradeon_common.c109 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); in radeonUpdateScissor() local
134 rmesa->state.scissor.rect.x1 = CLAMP(x1, min_x, max_x); in radeonUpdateScissor()
135 rmesa->state.scissor.rect.y1 = CLAMP(y1, min_y, max_y); in radeonUpdateScissor()
136 rmesa->state.scissor.rect.x2 = CLAMP(x2, min_x, max_x); in radeonUpdateScissor()
137 rmesa->state.scissor.rect.y2 = CLAMP(y2, min_y, max_y); in radeonUpdateScissor()
139 if (rmesa->vtbl.update_scissor) in radeonUpdateScissor()
140 rmesa->vtbl.update_scissor(ctx); in radeonUpdateScissor()
385 struct radeon_context *const rmesa = RADEON_CONTEXT(ctx); in radeonReadBuffer() local
386 const GLboolean was_front_buffer_reading = rmesa->is_front_buffer_reading; in radeonReadBuffer()
387 rmesa->is_front_buffer_reading = (mode == GL_FRONT_LEFT) in radeonReadBuffer()
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Dradeon_maos_verts.c312 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonEmitArrays() local
316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & in radeonEmitArrays()
359 if (((rmesa->NeedTexMatrix >> unit) & 1) && in radeonEmitArrays()
360 (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) in radeonEmitArrays()
361 radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; in radeonEmitArrays()
366 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { in radeonEmitArrays()
367 RADEON_STATECHANGE( rmesa, tcl ); in radeonEmitArrays()
368 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; in radeonEmitArrays()
375 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && in radeonEmitArrays()
376 rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
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Dradeon_tex.c261 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonTexEnv() local
276 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) { in radeonTexEnv()
277 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonTexEnv()
278 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor; in radeonTexEnv()
292 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? in radeonTexEnv()
302 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) { in radeonTexEnv()
303 RADEON_STATECHANGE( rmesa, tex[unit] ); in radeonTexEnv()
304 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK; in radeonTexEnv()
305 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK); in radeonTexEnv()
357 r100ContextPtr rmesa = R100_CONTEXT(ctx); in radeonDeleteTexture() local
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