| /external/gemmlowp/meta/generators/ |
| D | neon_emitter.py | 323 def EmitVShl(self, shift_type, destination, source, shift): argument
324 self.EmitOp3('vshl.%s' % shift_type, destination, source, shift)
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| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 913 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) { in ShiftOperand() argument
920 switch (shift_type) { in ShiftOperand()
1417 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitAddSubShifted() local
1421 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitAddSubShifted()
1425 ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount)); in VisitAddSubShifted()
1464 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitLogicalShifted() local
1468 int64_t op2 = ShiftOperand(xreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1472 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
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| D | disasm-arm64.cc | 1522 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; in SubstituteShiftField() local
1523 AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()], in SubstituteShiftField()
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| D | simulator-arm64.h | 697 Shift shift_type,
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 317 Shift shift_type, in ShiftOperand() argument
323 switch (shift_type) { in ShiftOperand()
966 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); in VisitLogicalShifted() local
968 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type, in VisitLogicalShifted()
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| D | simulator-a64.h | 1315 Shift shift_type,
1319 Shift shift_type,
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| D | disasm-a64.cc | 3247 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; in SubstituteShiftField() local
3248 AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()], in SubstituteShiftField()
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| /external/valgrind/VEX/priv/ |
| D | guest_arm_toIR.c | 9066 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; in decode_V6MEDIA_instruction() local
9077 shift_type = (INSNT1(5,5) << 1) | 0; in decode_V6MEDIA_instruction()
9090 shift_type = (INSNA(6,6) << 1) | 0; in decode_V6MEDIA_instruction()
9102 dis_buf, &irt_regM_shift, NULL, irt_regM, shift_type, imm5, regM ); in decode_V6MEDIA_instruction()
9126 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; in decode_V6MEDIA_instruction() local
9135 shift_type = (INSNT0(5,5) << 1) | 0; in decode_V6MEDIA_instruction()
9140 if (shift_type == BITS2(1,0) && imm5 == 0) in decode_V6MEDIA_instruction()
9148 shift_type = (INSNA(6,6) << 1) | 0; in decode_V6MEDIA_instruction()
9165 irt_regN, shift_type, imm5, regN ); in decode_V6MEDIA_instruction()
9184 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; in decode_V6MEDIA_instruction() local
[all …]
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| /external/v8/src/arm/ |
| D | simulator-arm.cc | 2672 int32_t shift_type = instr->Bit(6); in DecodeType3() local
2674 if (shift_type == 0) { // LSL in DecodeType3()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1399 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1403 let Inst{11-10} = shift_type;
1406 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1407 def Wr : BaseShift<shift_type, GPR32, asm> {
1411 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
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