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/external/llvm/test/CodeGen/X86/
Dssse3-intrinsics-x86.ll1 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+ssse3 | FileCheck %s
5 %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
8 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
13 %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
16 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
21 %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1]
24 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
29 …%res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#us…
32 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
37 …%res = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#u…
[all …]
Dssse3-intrinsics-fast-isel.ll1 ; RUN: llc < %s -fast-isel -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix…
2 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-pref…
4 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/ssse3-builtins.c
17 %call = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %arg)
21 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
34 %call = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %arg)
38 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
51 %call = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %arg)
55 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
88 %call = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %arg0, <8 x i16> %arg1)
[all …]
Dpshufb-mask-comments.ll1 ; RUN: llc < %s -march=x86-64 -mattr=+ssse3 | FileCheck %s
8 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8…
17 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 15, i8 0, i8 0, i…
26 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8…
36 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> undef, <16 x i8> <i8 8, i8 9, i8 10…
48 %2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> undef, <16 x i8> %1)
52 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
Dx86-fold-pshufb.ll2 ; RUN: llc -relocation-model=pic -march=x86-64 -mtriple=x86_64-unknown-unknown -mattr=+ssse3 < %s |…
3 ; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-unknown -mattr=+ssse3 < %s | FileCheck %s
14 …%0 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 0…
30 …%0 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 …
35 declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>)
Dstack-folding-mmx.ll1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+ssse3 | FileCheck %s
66 %2 = call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %a0) nounwind readnone
69 declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
75 %2 = call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %a0) nounwind readnone
78 declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
84 %2 = call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %a0) nounwind readnone
87 declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
291 %2 = call x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx %a, x86_mmx %b) nounwind readnone
294 declare x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx, x86_mmx) nounwind readnone
300 %2 = call x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx %a, x86_mmx %b) nounwind readnone
[all …]
Dv4i32load-crash.ll1 ; RUN: llc --march=x86 --mcpu=x86-64 --mattr=ssse3 < %s
2 ; RUN: llc --march=x86-64 --mcpu=x86-64 --mattr=ssse3 < %s
Dmmx-intrinsics.ll1 ; RUN: llc < %s -march=x86 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix…
3 ; RUN: llc < %s -march=x86-64 -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-pre…
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
1206 declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone
1214 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx %1) nounwind readnone
1221 declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone
1229 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx %1) nounwind readnone
1236 declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone
1244 %2 = tail call x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx %1) nounwind readnone
[all …]
Dstack-folding-int-avx1.ll118 %2 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0)
121 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
127 %2 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0)
130 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
136 %2 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0)
139 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
453 %2 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1)
456 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
462 %2 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1)
465 declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
[all …]
Dstack-folding-int-sse42.ll145 %2 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0)
148 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
154 %2 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0)
157 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
163 %2 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0)
166 declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
480 %2 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1)
483 declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone
489 %2 = call <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16> %a0, <8 x i16> %a1)
492 declare <8 x i16> @llvm.x86.ssse3.phadd.sw.128(<8 x i16>, <8 x i16>) nounwind readnone
[all …]
/external/llvm/test/Bitcode/
Dssse3_palignr.ll9 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i…
18 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> …
24 declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
30 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>>…
40 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> …
50 …%2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> …
60 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i…
65 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
71 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i…
80 …%2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i…
/external/skia/src/opts/
Dopts_check_x86.cpp139 const bool ssse3 = supports_simd(SK_CPU_SSE_LEVEL_SSSE3); in platformProcs() local
143 if (ssse3) { in platformProcs()
149 if (ssse3) { in platformProcs()
153 if (ssse3) { in platformProcs()
159 if (ssse3) { in platformProcs()
/external/llvm/test/Transforms/InstCombine/
Dx86-pshufb.ll9 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
28 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
47 %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> zeroinitializer)
71 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 1, i…
79 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
87 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
95 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128…
103 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
111 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 -…
168 …%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2…
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dvariance_sse2.c328 DECLS(ssse3, ssse3);
387 FNS(ssse3, ssse3);
409 DECLS(ssse3, ssse3);
473 FNS(ssse3, ssse3);
Dintrapred_ssse3.asm36 INIT_MMX ssse3
54 INIT_MMX ssse3
72 INIT_XMM ssse3
90 INIT_XMM ssse3
110 INIT_MMX ssse3
137 INIT_MMX ssse3
176 INIT_XMM ssse3
227 INIT_XMM ssse3
322 INIT_XMM ssse3
344 INIT_XMM ssse3
[all …]
Dsubpel_variance_sse2.asm106 %if cpuflag(ssse3)
113 ; FIXME(rbultje) only bilinear filters use >8 registers, and ssse3 only uses
381 %if cpuflag(ssse3)
427 %if cpuflag(ssse3)
650 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
827 %if cpuflag(ssse3)
869 %if cpuflag(ssse3)
930 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
1123 %if notcpuflag(ssse3) ; FIXME(rbultje) don't scatter registers on x86-64
/external/flac/libFLAC/
Dcpu.c52 info->ia32.ssse3 = false; in disable_sse()
180 info->ia32.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false; in FLAC__cpu_info()
199 fprintf(stderr, " SSSE3 ...... %c\n", info->ia32.ssse3 ? 'Y' : 'n'); in FLAC__cpu_info()
358 info->x86.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false; in FLAC__cpu_info()
372 fprintf(stderr, " SSSE3 ...... %c\n", info->x86.ssse3 ? 'Y' : 'n'); in FLAC__cpu_info()
/external/flac/libFLAC/include/private/
Dcpu.h127 FLAC__bool ssse3; member
139 FLAC__bool ssse3; member
/external/clang/include/clang/Basic/
DBuiltinsX86.def167 TARGET_BUILTIN(__builtin_ia32_pabsb, "V8cV8c", "", "ssse3")
168 TARGET_BUILTIN(__builtin_ia32_pabsd, "V2iV2i", "", "ssse3")
169 TARGET_BUILTIN(__builtin_ia32_pabsw, "V4sV4s", "", "ssse3")
170 TARGET_BUILTIN(__builtin_ia32_palignr, "V8cV8cV8cIc", "", "ssse3")
171 TARGET_BUILTIN(__builtin_ia32_phaddd, "V2iV2iV2i", "", "ssse3")
172 TARGET_BUILTIN(__builtin_ia32_phaddsw, "V4sV4sV4s", "", "ssse3")
173 TARGET_BUILTIN(__builtin_ia32_phaddw, "V4sV4sV4s", "", "ssse3")
174 TARGET_BUILTIN(__builtin_ia32_phsubd, "V2iV2iV2i", "", "ssse3")
175 TARGET_BUILTIN(__builtin_ia32_phsubsw, "V4sV4sV4s", "", "ssse3")
176 TARGET_BUILTIN(__builtin_ia32_phsubw, "V4sV4sV4s", "", "ssse3")
[all …]
/external/valgrind/none/tests/amd64/
Dssse3_misaligned.vgtest2 prereq: ../../../tests/x86_amd64_features amd64-ssse3
Dinsn_ssse3.vgtest2 prereq: ../../../tests/x86_amd64_features amd64-ssse3
/external/valgrind/none/tests/x86/
Dssse3_misaligned.vgtest2 prereq: test -x ssse3_misaligned && ../../../tests/x86_amd64_features x86-ssse3
Dinsn_ssse3.vgtest2 prereq: test -x insn_ssse3 && ../../../tests/x86_amd64_features x86-ssse3
/external/clang/lib/Headers/
Dmodule.modulemap62 explicit module ssse3 {
68 export ssse3
/external/llvm/test/Instrumentation/MemorySanitizer/
Dvector_arith.ll7 declare x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx, x86_mmx) nounwind readnone
27 %c = tail call x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx %a, x86_mmx %b) nounwind
/external/llvm/test/Other/
Dopt-override-mcpu-mattr.ll13 attributes #0 = { nounwind readnone ssp uwtable "target-cpu"="core2" "target-features"="+ssse3,+cx1…

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