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/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_cmdbuf.c75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); in r200SetUpAtomList()
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); in r200FireEB()
154 rmesa->radeon.tcl.elt_dma_bo, in r200FireEB()
163 int nr, elt_used = rmesa->tcl.elt_used; in r200FlushElts()
165 …radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, e… in r200FlushElts()
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); in r200FlushElts()
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); in r200FlushElts()
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); in r200FlushElts()
177 rmesa->radeon.tcl.elt_dma_bo = NULL; in r200FlushElts()
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, in r200AllocEltsOpenEnded()
[all …]
Dr200_state.c390 R200_STATECHANGE(rmesa, tcl); in r200Fogfv()
391 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; in r200Fogfv()
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR; in r200Fogfv()
405 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP; in r200Fogfv()
410 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2; in r200Fogfv()
496 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; in r200CullFace()
523 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) { in r200CullFace()
524 R200_STATECHANGE(rmesa, tcl ); in r200CullFace()
525 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t; in r200CullFace()
537 R200_STATECHANGE( rmesa, tcl ); in r200FrontFace()
[all …]
Dr200_maos_arrays.c117 if (!rmesa->radeon.tcl.aos[i].bo) { in r200EmitArrays()
120 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
127 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
176 if (!rmesa->radeon.tcl.aos[nr].bo) { in r200EmitArrays()
178 &(rmesa->radeon.tcl.aos[nr]), in r200EmitArrays()
197 rmesa->radeon.tcl.aos_count = nr; in r200EmitArrays()
Dr200_tcl.c145 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { in r200AllocElts()
147 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr + in r200AllocElts()
148 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used); in r200AllocElts()
150 rmesa->tcl.elt_used += nr*2; in r200AllocElts()
159 rmesa->radeon.tcl.aos_count, 0 ); in r200AllocElts()
161 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count); in r200AllocElts()
162 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); in r200AllocElts()
190 rmesa->radeon.tcl.aos_count, in r200EmitPrim()
196 rmesa->tcl.hw_primitive, in r200EmitPrim()
213 rmesa->tcl.hw_primitive == (PRIM| \
[all …]
Dr200_state_init.c263 TCL_CHECK( tcl, GL_TRUE, 0 )
705 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 ); in r200InitState()
706 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); in r200InitState()
707 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); in r200InitState()
805 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0); in r200InitState()
806 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL); in r200InitState()
1170 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = in r200InitState()
1177 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = in r200InitState()
1187 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ in r200InitState()
1188 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; in r200InitState()
[all …]
Dradeon_dma.c504 for (i = 0; i < radeon->tcl.aos_count; i++) { in radeonReleaseArrays()
505 if (radeon->tcl.aos[i].bo) { in radeonReleaseArrays()
506 radeon_bo_unref(radeon->tcl.aos[i].bo); in radeonReleaseArrays()
507 radeon->tcl.aos[i].bo = NULL; in radeonReleaseArrays()
Dr200_context.h492 struct radeon_state_atom tcl; member
614 struct r200_tcl_info tcl; member
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c77 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); in radeonSetUpAtomList()
174 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); in radeonFlushElts()
183 nr = rmesa->tcl.elt_used; in radeonFlushElts()
233 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; in radeonAllocEltsOpenEnded()
260 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; in radeonAllocEltsOpenEnded()
261 rmesa->tcl.elt_used = min_nr; in radeonAllocEltsOpenEnded()
263 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); in radeonAllocEltsOpenEnded()
308 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; in radeonEmitAOS()
310 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); in radeonEmitAOS()
311 rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count; in radeonEmitAOS()
[all …]
Dradeon_maos_verts.c316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & in radeonEmitArrays()
366 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) { in radeonEmitArrays()
367 RADEON_STATECHANGE( rmesa, tcl ); in radeonEmitArrays()
368 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx; in radeonEmitArrays()
375 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format && in radeonEmitArrays()
376 rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
379 if (rmesa->radeon.tcl.aos[0].bo) in radeonEmitArrays()
383 &rmesa->radeon.tcl.aos[0].bo, in radeonEmitArrays()
384 &rmesa->radeon.tcl.aos[0].offset, in radeonEmitArrays()
396 _math_trans_4f( rmesa->tcl.ObjClean.data, in radeonEmitArrays()
[all …]
Dradeon_maos_arrays.c159 if (!rmesa->tcl.obj.buf) in radeonEmitArrays()
161 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
179 if (!rmesa->tcl.norm.buf) in radeonEmitArrays()
181 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
205 if (!rmesa->tcl.rgba.buf) in radeonEmitArrays()
207 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
218 if (!rmesa->tcl.spec.buf) { in radeonEmitArrays()
221 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
236 if (!rmesa->tcl.fog.buf) in radeonEmitArrays()
238 &(rmesa->tcl.aos[nr]), in radeonEmitArrays()
[all …]
Dradeon_state.c325 RADEON_STATECHANGE(rmesa, tcl); in radeonFogfv()
326 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK; in radeonFogfv()
329 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR; in radeonFogfv()
332 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP; in radeonFogfv()
335 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2; in radeonFogfv()
404 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; in radeonCullFace()
431 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) { in radeonCullFace()
432 RADEON_STATECHANGE(rmesa, tcl ); in radeonCullFace()
433 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t; in radeonCullFace()
445 RADEON_STATECHANGE( rmesa, tcl ); in radeonFrontFace()
[all …]
Dradeon_tcl.c114 #define GET_MESA_ELTS() rmesa->tcl.Elts
153 rmesa->radeon.tcl.aos_count, 0 ); in radeonAllocElts()
155 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format, in radeonAllocElts()
156 rmesa->tcl.hw_primitive, nr ); in radeonAllocElts()
177 rmesa->radeon.tcl.aos_count, in radeonEmitPrim()
183 rmesa->tcl.vertex_format, in radeonEmitPrim()
184 rmesa->tcl.hw_primitive, in radeonEmitPrim()
202 rmesa->tcl.hw_primitive == (PRIM| \
259 if (newprim != rmesa->tcl.hw_primitive || in radeonTclPrimitive()
262 rmesa->tcl.hw_primitive = newprim; in radeonTclPrimitive()
[all …]
Dradeon_state_init.c541 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 ); in radeonInitState()
612 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); in radeonInitState()
831 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = in radeonInitState()
837 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] = in radeonInitState()
845 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] = in radeonInitState()
849 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] = in radeonInitState()
855 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = in radeonInitState()
859 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0; in radeonInitState()
861 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] = in radeonInitState()
Dradeon_context.h314 struct radeon_state_atom tcl; member
423 struct r100_tcl_info tcl; member
Dradeon_dma.c504 for (i = 0; i < radeon->tcl.aos_count; i++) { in radeonReleaseArrays()
505 if (radeon->tcl.aos[i].bo) { in radeonReleaseArrays()
506 radeon_bo_unref(radeon->tcl.aos[i].bo); in radeonReleaseArrays()
507 radeon->tcl.aos[i].bo = NULL; in radeonReleaseArrays()
Dradeon_texstate.c745 RADEON_STATECHANGE( rmesa, tcl ); in disable_tex_obj_state()
746 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) | in disable_tex_obj_state()
917 RADEON_STATECHANGE( rmesa, tcl ); in radeon_validate_texgen()
918 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit); in radeon_validate_texgen()
1075 RADEON_STATECHANGE( rmesa, tcl ); in radeon_validate_texture()
1076 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit); in radeon_validate_texture()
Dradeon_context.c129 _mesa_vector4f_free( &rmesa->tcl.ObjClean ); in r100_vtbl_free_context()
383 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, in r100CreateContext()
/external/google-breakpad/src/third_party/libdisasm/swig/
DMakefile16 dummy: swig swig-python swig-ruby swig-perl swig-tcl install uninstall clean
30 swig-tcl:
31 cd tcl && make -f Makefile-swig
46 install-tcl:
47 cd tcl && sudo make -f Makefile-swig install
62 uninstall-tcl:
63 cd tcl && sudo make -f Makefile-swig uninstall
70 cd tcl && make -f Makefile-swig clean
/external/google-breakpad/src/third_party/libdisasm/swig/tcl/
DMakefile-swig27 TCL_MOD = $(BASE_NAME)-tcl.so
30 TCL_INC = /usr/include/tcl$(TCL_VERSION)
31 TCL_LIB = /usr/lib/tcl$(TCL_VERSION)
37 all: swig-tcl
39 dummy: swig-tcl install uninstall clean
41 swig-tcl: $(TCL_MOD)
50 swig -tcl -o $(TCL_SHADOW) -outdir . $<
/external/eigen/cmake/
DEigenConfigureTesting.cmake18 # so we have to workaround by directly editing the generated DartConfiguration.tcl file
24 # This call activates testing and generates the DartConfiguration.tcl
29 # overwrite default DartConfiguration.tcl
44 …re_file(${CMAKE_CURRENT_BINARY_DIR}/DartConfiguration.tcl ${CMAKE_BINARY_DIR}/DartConfiguration.tc…
/external/clang/test/Modules/
Ddarwin_specific_modulemap_hacks.m12 #error tcl-private/header.h should be textual
16 #import <tcl-private/header.h>
21 #error tcl-private/header.h missing
/external/sl4a/ScriptingLayerForAndroid/res/drawable/
Datari_small_notice.txt10 COMMENT Produced with bdfedit, a tcl/tk font editing program
/external/google-breakpad/src/third_party/libdisasm/
DMakefile.am42 swig/tcl/Makefile-swig \
/external/jetty/src/resources/org/eclipse/jetty/http/
Dmime.properties146 tcl = application/x-tcl key
/external/opencv3/3rdparty/zlib/
DREADME49 zlib is built into tcl: http://wiki.tcl.tk/4610 .

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