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Searched refs:wreg (Results 1 – 12 of 12) sorted by relevance

/external/vixl/examples/
Dswap-int32.cc85 simulator.wreg(0), simulator.wreg(1)); in main()
92 simulator.wreg(0), simulator.wreg(1)); in main()
Dcrc-checksums.cc89 printf("crc32(\"%s\")=0x%x\n", msg, simulator.wreg(0)); in runExample()
Dsum-array.cc87 printf("%d = %d\n", data[i], simulator.wreg(0)); in main()
/external/v8/src/arm64/
Dsimulator-arm64.cc684 TraceSim("Arguments: %f, %d\n", dreg(0), wreg(0)); in DoRuntimeCall()
685 double result = target(dreg(0), wreg(0)); in DoRuntimeCall()
1375 case CBZ_w: take_branch = (wreg(rt) == 0); break; in VisitCompareBranch()
1377 case CBNZ_w: take_branch = (wreg(rt) != 0); break; in VisitCompareBranch()
1425 ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount)); in VisitAddSubShifted()
1448 int32_t op2 = ExtendValue(wreg(instr->Rm()), ext, left_shift); in VisitAddSubExtended()
1472 int32_t op2 = ShiftOperand(wreg(instr->Rm()), shift_type, shift_amount); in VisitLogicalShifted()
1521 ConditionalCompareHelper(instr, wreg(instr->Rm())); in VisitConditionalCompareRegister()
1626 case STRB_w: MemoryWrite<uint8_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
1627 case STRH_w: MemoryWrite<uint16_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
[all …]
Dsimulator-arm64.h343 int32_t wreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc876 case CBZ_w: take_branch = (wreg(rt) == 0); break; in VisitCompareBranch()
878 case CBNZ_w: take_branch = (wreg(rt) != 0); break; in VisitCompareBranch()
1114 case STRB_w: Memory::Write<uint8_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
1115 case STRH_w: Memory::Write<uint16_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
1116 case STR_w: Memory::Write<uint32_t>(address, wreg(srcdst)); break; in LoadStoreHelper()
1222 Memory::Write<uint32_t>(address, wreg(rt)); in LoadStorePairHelper()
1223 Memory::Write<uint32_t>(address2, wreg(rt2)); in LoadStorePairHelper()
1404 Memory::Write<uint8_t>(address, wreg(rt)); in VisitLoadStoreExclusive()
1409 Memory::Write<uint16_t>(address, wreg(rt)); in VisitLoadStoreExclusive()
1414 Memory::Write<uint32_t>(address, wreg(rt)); in VisitLoadStoreExclusive()
[all …]
Dsimulator-a64.h745 int32_t wreg(unsigned code,
/external/v8/test/cctest/
Dtest-utils-arm64.h58 inline int32_t wreg(unsigned code) const { in wreg() function
Dtest-utils-arm64.cc107 uint32_t result_w = core->wreg(reg.code()); in Equal32()
/external/vixl/test/
Dtest-utils-a64.h79 inline int32_t wreg(unsigned code) const { in wreg() function
Dtest-utils-a64.cc130 uint32_t result_w = core->wreg(reg.code()); in Equal32()
/external/vixl/test/examples/
Dtest-examples.cc490 assert(regs.wreg(0) == y); in TEST()
491 assert(regs.wreg(1) == x); in TEST()