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/external/llvm/test/CodeGen/ARM/
Datomic-64bit.ll14 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
22 ; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
23 ; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
24 ; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
25 ; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]
26 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
43 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
51 ; CHECK-THUMB-LE: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
[all …]
/external/llvm/test/CodeGen/Mips/
Dreturn-vector.ll36 ; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
37 ; CHECK: lw $[[R1:[a-z0-9]+]], 56($sp)
38 ; CHECK: lw $[[R2:[a-z0-9]+]], 52($sp)
39 ; CHECK: lw $[[R3:[a-z0-9]+]], 48($sp)
40 ; CHECK: lw $[[R4:[a-z0-9]+]], 44($sp)
41 ; CHECK: lw $[[R5:[a-z0-9]+]], 40($sp)
42 ; CHECK: lw $[[R6:[a-z0-9]+]], 36($sp)
43 ; CHECK: lw $[[R7:[a-z0-9]+]], 32($sp)
62 ; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
63 ; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp)
[all …]
Dbiggot.ll10 ; O32: addu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
13 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
17 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}}
20 ; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
36 ; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
41 ; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
/external/llvm/test/Transforms/InstCombine/
Dabs_abs.ll12 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, -1
13 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x
14 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]]
27 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp sgt i32 %x, 0
28 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x
29 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 %x, i32 [[NEG]]
42 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 0
43 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub nsw i32 0, %x
44 ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[NEG]], i32 %x
57 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp slt i32 %x, 1
[all …]
Dunpack-fca.ll16 ; CHECK-NEXT: [[GEP:%[a-z0-9\.]+]] = getelementptr inbounds %A, %A* %a.ptr, i64 0, i32 0
25 ; CHECK-NEXT: [[GEP1:%[a-z0-9\.]+]] = getelementptr inbounds %B, %B* %b.ptr, i64 0, i32 0
27 ; CHECK-NEXT: [[GEP2:%[a-z0-9\.]+]] = getelementptr inbounds %B, %B* %b.ptr, i64 0, i32 1
36 ; CHECK-NEXT: [[GEP:%[a-z0-9\.]+]] = getelementptr inbounds { %A }, { %A }* %sa.ptr, i64 0, i32 0, …
45 ; CHECK-NEXT: [[GEP:%[a-z0-9\.]+]] = getelementptr inbounds [1 x %A], [1 x %A]* %aa.ptr, i64 0, i64…
54 ; CHECK-NEXT: [[GEP:%[a-z0-9\.]+]] = getelementptr inbounds { [1 x %A] }, { [1 x %A] }* %saa.ptr, i…
63 ; CHECK-NEXT: [[GEP:%[a-z0-9\.]+]] = getelementptr inbounds %A, %A* %a.ptr, i64 0, i32 0
64 ; CHECK-NEXT: [[LOAD:%[a-z0-9\.]+]] = load %A__vtbl*, %A__vtbl** [[GEP]], align 8
65 ; CHECK-NEXT: [[IV:%[a-z0-9\.]+]] = insertvalue %A undef, %A__vtbl* [[LOAD]], 0
73 ; CHECK-NEXT: [[GEP1:%[a-z0-9\.]+]] = getelementptr inbounds %B, %B* %b.ptr, i64 0, i32 0
[all …]
Dabs-1.ll16 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i32 %x, -1
17 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i32 0, %x
18 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i32 %x, i32 [[NEG]]
26 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
27 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
28 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
36 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
37 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
38 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[ISPOS]], i64 %x, i64 [[NEG]]
Dpow-1.ll40 ; CHECK-NEXT: [[EXP2F:%[a-z0-9]+]] = call float @exp2f(float %x) [[NUW_RO:#[0-9]+]]
48 ; CHECK-NEXT: [[EXP2:%[a-z0-9]+]] = call double @exp2(double %x) [[NUW_RO]]
74 ; CHECK-NEXT: [[SQRTF:%[a-z0-9]+]] = call float @sqrtf(float %x) [[NUW_RO]]
75 ; CHECK-NEXT: [[FABSF:%[a-z0-9]+]] = call float @fabsf(float [[SQRTF]]) [[NUW_RO]]
76 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq float %x, 0xFFF0000000000000
77 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], float 0x7FF0000000000000, float [[FABSF]]
85 ; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[NUW_RO]]
86 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
87 ; CHECK-NEXT: [[FCMP:%[a-z0-9]+]] = fcmp oeq double %x, 0xFFF0000000000000
88 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
[all …]
Dffs-1.ll108 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
109 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
110 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
111 ; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
119 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
120 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
121 ; CHECK-FFS-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0
122 ; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0
130 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
131 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
[all …]
Dsincospi.ll26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
31 ; CHECK: [[VAL:%[a-z0-9]+]] = load float, float* @var32
32 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float [[VAL]])
45 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+0…
49 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { float, float } @__sincospif_stret(float 1.000000e+00)
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VA…
68 ; CHECK: [[VAL:%[a-z0-9]+]] = load double, double* @var64
69 ; CHECK: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VAL]])
[all …]
Dadd2.ll99 ; CHECK-NEXT: [[SHR:%[a-z0-9]+]] = ashr i32 %x, 3
100 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHR]], 1431655765
101 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]]
113 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655765
114 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]]
126 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655765
127 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]]
139 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655766
140 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = sub i32 %y, [[AND]]
152 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 1431655766
[all …]
/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll7 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
27 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
47 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
67 ; SI: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
[all …]
/external/llvm/test/Transforms/LowerAtomic/
Datomic-swap.ll8 ; CHECK: [[OLDVAL:%[a-z0-9]+]] = load i8, i8* [[ADDR:%[a-z0-9]+]]
9 ; CHECK-NEXT: [[SAME:%[a-z0-9]+]] = icmp eq i8 [[OLDVAL]], 0
10 ; CHECK-NEXT: [[TO_STORE:%[a-z0-9]+]] = select i1 [[SAME]], i8 42, i8 [[OLDVAL]]
12 ; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = insertvalue { i8, i1 } undef, i8 [[OLDVAL]], 0
13 ; CHECK-NEXT: [[RES:%[a-z0-9]+]] = insertvalue { i8, i1 } [[TMP]], i1 [[SAME]], 1
14 ; CHECK-NEXT: [[VAL:%[a-z0-9]+]] = extractvalue { i8, i1 } [[RES]], 0
24 ; CHECK: [[INST:%[a-z0-9]+]] = load
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll8 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
27 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
47 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
67 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
87 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
[all …]
/external/llvm/test/CodeGen/X86/
Dhalf.ll10 ; CHECK: movw (%rdi), [[TMP:%[a-z0-9]+]]
85 ; CHECK-F16C-NEXT: movswl (%rdi), [[REG0:%[a-z0-9]+]]
86 ; CHECK-F16C-NEXT: vmovd [[REG0]], [[REG1:%[a-z0-9]+]]
87 ; CHECK-F16C-NEXT: vcvtph2ps [[REG1]], [[REG2:%[a-z0-9]+]]
106 ; CHECK-F16C-NEXT: vcvtsi2ssq %rdi, [[REG0:%[a-z0-9]+]], [[REG0]]
123 ; CHECK-LIBCALL-NEXT: movss {{.[A-Z_0-9]+}}(%rip), [[REG1:%[a-z0-9]+]]
124 ; CHECK-LIBCALL-NEXT: movaps %xmm0, [[REG2:%[a-z0-9]+]]
126 ; CHECK-LIBCALL-NEXT: cvttss2si [[REG2]], [[REG3:%[a-z0-9]+]]
127 ; CHECK-LIBCALL-NEXT: movabsq $-9223372036854775808, [[REG4:%[a-z0-9]+]]
129 ; CHECK-LIBCALL-NEXT: cvttss2si %xmm0, [[REG5:%[a-z0-9]+]]
[all …]
Dx86-64-psub.ll31 ; CHECK: movq %rax, [[TEMP:%[a-z0-9]+]]
33 ; CHECK: movd [[TEMP]], [[PARAM1:%[a-z0-9]+]]
34 ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
59 ; CHECK: movq %rax, [[TEMP:%[a-z0-9]+]]
61 ; CHECK: movd [[TEMP]], [[PARAM1:%[a-z0-9]+]]
62 ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
88 ; CHECK: movq %rax, [[TEMP:%[a-z0-9]+]]
90 ; CHECK: movd [[TEMP]], [[PARAM1:%[a-z0-9]+]]
91 ; CHECK: movd %rax, [[PARAM2:%[a-z0-9]+]]
116 ; CHECK: movq %rax, [[TEMP:%[a-z0-9]+]]
[all …]
/external/mesa3d/src/mesa/program/
Dprog_noise.c344 float z0 = z - Z0; in _mesa_noise3() local
357 if (y0 >= z0) { in _mesa_noise3()
365 else if (x0 >= z0) { in _mesa_noise3()
383 if (y0 < z0) { in _mesa_noise3()
391 else if (x0 < z0) { in _mesa_noise3()
417 z1 = z0 - k1 + G3; in _mesa_noise3()
420 z2 = z0 - k2 + 2.0f * G3; in _mesa_noise3()
423 z3 = z0 - 1.0f + 3.0f * G3; in _mesa_noise3()
431 t0 = 0.6f - x0 * x0 - y0 * y0 - z0 * z0; in _mesa_noise3()
436 n0 = t0 * t0 * grad3(perm[ii + perm[jj + perm[kk]]], x0, y0, z0); in _mesa_noise3()
[all …]
/external/llvm/test/Transforms/SimplifyCFG/AArch64/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/Mips/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/ARM/
Dcttz-ctlz.ll5 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
6 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
7 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
24 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
25 ; CHECK-NEXT: [[CTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
26 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTZ]]
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll7 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
26 ; CHECK: [[ICMP:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/llvm/test/MC/Mips/
Dsext_64_32.ll5 ; CHECK: sll ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
13 ; CHECK: dsll32 ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0
/external/llvm/test/CodeGen/PowerPC/
Dmcm-4.ll17 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
24 ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
31 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
34 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
38 ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
41 ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
/external/mesa3d/src/gallium/drivers/softpipe/
Dsp_quad_depth_test_tmp.h60 const float z0 = quads[0]->posCoef->a0[2] + dzdx * fx + dzdy * fy; in NAME() local
67 init_idepth[0] = (ushort)((z0) * scale); in NAME()
68 init_idepth[1] = (ushort)((z0 + dzdx) * scale); in NAME()
69 init_idepth[2] = (ushort)((z0 + dzdy) * scale); in NAME()
70 init_idepth[3] = (ushort)((z0 + dzdx + dzdy) * scale); in NAME()
/external/aac/libAACdec/src/
Dldfiltbank.cpp111 FIXP_DBL z0, z2, tmp; in multE2_DinvF_fdk() local
114 z0 = z2 + ( fMultDiv2(z[N/2+i], fb[2*N + i]) >> (-WTS2-1) ); in multE2_DinvF_fdk()
128 z[i] = z0; in multE2_DinvF_fdk()
134 FIXP_DBL z0, z2, tmp0, tmp1; in multE2_DinvF_fdk() local
137 z0 = z2 + ( fMultDiv2(z[N/2+i], fb[2*N + i]) >> (-WTS2-1) ); in multE2_DinvF_fdk()
153 z[i] = z0; in multE2_DinvF_fdk()
/external/aac/libAACenc/src/
Dtransform.cpp222 FIXP_DBL z0, outval; in FDKaacEnc_Transform_Real() local
224 …z0 = (fMult((FIXP_PCM)timeData[L+N*3/4-1-i], pWindowELD[N/2-1-i])<< (WTS0-1)) + (fMult((FIXP_PCM)t… in FDKaacEnc_Transform_Real()
232 overlapAddBuffer[i] = z0; in FDKaacEnc_Transform_Real()
241 FIXP_DBL z0, outval; in FDKaacEnc_Transform_Real() local
243 z0 = fMult((FIXP_PCM)timeData[L+N*3/4-1-i], pWindowELD[N/2-1-i]) << (WTS0-1); in FDKaacEnc_Transform_Real()
250 overlapAddBuffer[i] = z0; in FDKaacEnc_Transform_Real()

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