| /external/mesa3d/src/mesa/sparc/ |
| D | norm.S | 86 fsqrts %f6, %f6 ! FDIV 20 cycles
87 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
213 fsqrts %f6, %f6 ! FDIV 20 cycles
214 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
517 fsqrts %f6, %f6 ! FDIV 20 cycles
518 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
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| /external/javassist/src/main/javassist/bytecode/ |
| D | Opcode.java | 95 int FDIV = 110; field
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| D | Opcodes.java | 249 int FDIV = 110; // - field
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| D | Frame.java | 1090 case Opcodes.FDIV: in execute()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| /external/valgrind/none/tests/ppc64/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
1009 case FDIV: in check_double_guarded_arithmetic_op()
1135 case FDIV: in check_double_guarded_arithmetic_op()
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| /external/valgrind/none/tests/ppc32/ |
| D | round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD, enumerator
1009 case FDIV: in check_double_guarded_arithmetic_op()
1135 case FDIV: in check_double_guarded_arithmetic_op()
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| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| D | BasicInterpreter.java | 250 case FDIV: in binaryOperation()
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| D | BasicVerifier.java | 252 case FDIV: in binaryOperation()
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| D | Frame.java | 438 case Opcodes.FDIV: in execute()
|
| /external/v8/src/ppc/ |
| D | constants-ppc.h | 268 FDIV = 18 << 1, // Floating Divide enumerator
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| D | disasm-ppc.cc | 905 case FDIV: { in DecodeExt4()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1082 FDIV = FPDataProcessing2SourceFixed | 0x00001000, enumerator
1083 FDIV_s = FDIV,
1084 FDIV_d = FDIV | FP64,
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 670 X86_INTRINSIC_DATA(avx512_mask_div_pd_128, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
671 X86_INTRINSIC_DATA(avx512_mask_div_pd_256, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
672 X86_INTRINSIC_DATA(avx512_mask_div_pd_512, INTR_TYPE_2OP_MASK, ISD::FDIV,
674 X86_INTRINSIC_DATA(avx512_mask_div_ps_128, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
675 X86_INTRINSIC_DATA(avx512_mask_div_ps_256, INTR_TYPE_2OP_MASK, ISD::FDIV, 0),
676 X86_INTRINSIC_DATA(avx512_mask_div_ps_512, INTR_TYPE_2OP_MASK, ISD::FDIV,
678 X86_INTRINSIC_DATA(avx512_mask_div_sd_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FDIV,
680 X86_INTRINSIC_DATA(avx512_mask_div_ss_round, INTR_TYPE_SCALAR_MASK_RM, ISD::FDIV,
|
| /external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
| D | LabelFlowAnalyzerTest.java | 202 testInsn(FDIV, true); in testInsn()
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 1192 FDIV = FPDataProcessing2SourceFixed | 0x00001000, enumerator
1193 FDIV_s = FDIV,
1194 FDIV_d = FDIV | FP64,
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 199 case ISD::FDIV: return "fdiv"; in getOperationName()
|
| D | SelectionDAGBuilder.h | 786 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| D | LegalizeFloatTypes.cpp | 83 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1005 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
1870 case ISD::FDIV: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 273 case ISD::FDIV: in LegalizeOp()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 884 case ISD::FDIV: in canOpTrap()
1562 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 251 setOperationAction(ISD::FDIV, MVT::f32, Custom); in SITargetLowering()
252 setOperationAction(ISD::FDIV, MVT::f64, Custom); in SITargetLowering()
968 case ISD::FDIV: return LowerFDIV(Op, DAG); in LowerOperation()
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| /external/javassist/src/main/javassist/bytecode/analysis/ |
| D | Executor.java | 348 case FDIV: in execute()
|
| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 87 #define FDIV 0x1e601800 macro
1759 FAIL_IF(push_inst(compiler, (FDIV ^ inv_bits) | VD(dst_r) | VN(src1) | VM(src2))); in sljit_emit_fop2()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 153 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
282 setOperationAction(ISD::FDIV, MVT::f16, Promote); in AArch64TargetLowering()
315 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
321 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
362 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
486 setTargetDAGCombine(ISD::FDIV); in AArch64TargetLowering()
535 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
2285 case ISD::FDIV: in LowerOperation()
9618 case ISD::FDIV: in PerformDAGCombine()
|