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Searched refs:s64 (Results 1 – 25 of 83) sorted by relevance

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/external/v8/test/unittests/base/
Ddivision-by-constant-unittest.cc37 static M64 s64(int64_t d) { in s64() function
91 EXPECT_EQ(M64(0x9999999999999999ULL, 1, false), s64(-5)); in TEST()
92 EXPECT_EQ(M64(0x5555555555555555ULL, 1, false), s64(-3)); in TEST()
96 EXPECT_EQ(M64(0x7FFFFFFFFFFFFFFFULL, k - 1, false), s64(d)); in TEST()
99 EXPECT_EQ(M64(0x8000000000000001ULL, k - 1, false), s64(1LL << k)); in TEST()
101 EXPECT_EQ(M64(0x5555555555555556ULL, 0, false), s64(3)); in TEST()
102 EXPECT_EQ(M64(0x6666666666666667ULL, 1, false), s64(5)); in TEST()
103 EXPECT_EQ(M64(0x2AAAAAAAAAAAAAABULL, 0, false), s64(6)); in TEST()
104 EXPECT_EQ(M64(0x4924924924924925ULL, 1, false), s64(7)); in TEST()
105 EXPECT_EQ(M64(0x1C71C71C71C71C72ULL, 0, false), s64(9)); in TEST()
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv8.1a.txt5 [0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
7 [0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
10 [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
12 [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
18 # CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
24 # CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
30 # CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
36 # CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
40 [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0]
42 [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0]
[all …]
Dinvalid-armv8.1a.txt9 [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2
11 # CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2
19 [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0
21 # CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0
29 [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2
31 # CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2
39 [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2
41 # CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2
49 [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0]
51 # CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0]
[all …]
/external/llvm/test/MC/ARM/
Dneont2-satshift-encoding.s11 @ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0x71,0xef,0xb0,0x04]
12 vqshl.s64 d16, d16, d17
27 @ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0x72,0xef,0xf0,0x04]
28 vqshl.s64 q8, q8, q9
43 @ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xff,0xef,0xb0,0x07]
44 vqshl.s64 d16, d16, #63
59 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xff,0xff,0xb0,0x06]
60 vqshlu.s64 d16, d16, #63
67 @ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xff,0xef,0xf0,0x07]
68 vqshl.s64 q8, q8, #63
[all …]
Dneon-satshift-encoding.s9 @ CHECK: vqshl.s64 d16, d16, d17 @ encoding: [0xb0,0x04,0x71,0xf2]
10 vqshl.s64 d16, d16, d17
25 @ CHECK: vqshl.s64 q8, q8, q9 @ encoding: [0xf0,0x04,0x72,0xf2]
26 vqshl.s64 q8, q8, q9
41 @ CHECK: vqshl.s64 d16, d16, #63 @ encoding: [0xb0,0x07,0xff,0xf2]
42 vqshl.s64 d16, d16, #63
57 @ CHECK: vqshlu.s64 d16, d16, #63 @ encoding: [0xb0,0x06,0xff,0xf3]
58 vqshlu.s64 d16, d16, #63
65 @ CHECK: vqshl.s64 q8, q8, #63 @ encoding: [0xf0,0x07,0xff,0xf2]
66 vqshl.s64 q8, q8, #63
[all …]
Dneon-shift-encoding.s50 vshr.s64 d16, d16, #63
54 vshr.s64 q8, q8, #63
67 @ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2]
71 @ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2]
85 vshr.s64 d16, #63
89 vshr.s64 q8, #63
102 @ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2]
106 @ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2]
112 vsra.s64 d12, d19, #63
116 vsra.s64 q4, q5, #63
[all …]
Dneon-shiftaccum-encoding.s6 vsra.s64 d11, d10, #64
10 vsra.s64 q8, q4, #64
24 vsra.s64 d10, #64
28 vsra.s64 q4, #64
41 @ CHECK: vsra.s64 d11, d10, #64 @ encoding: [0x9a,0xb1,0x80,0xf2]
45 @ CHECK: vsra.s64 q8, q4, #64 @ encoding: [0xd8,0x01,0xc0,0xf2]
58 @ CHECK: vsra.s64 d10, d10, #64 @ encoding: [0x9a,0xa1,0x80,0xf2]
62 @ CHECK: vsra.s64 q4, q4, #64 @ encoding: [0xd8,0x81,0x80,0xf2]
75 vrsra.s64 d14, d23, #64
83 vrsra.s64 q4, q5, #64
[all …]
Dneont2-shiftaccum-encoding.s8 vsra.s64 d11, d10, #64
12 vsra.s64 q8, q4, #64
26 vsra.s64 d10, #64
30 vsra.s64 q4, #64
43 @ CHECK: vsra.s64 d11, d10, #64 @ encoding: [0x80,0xef,0x9a,0xb1]
47 @ CHECK: vsra.s64 q8, q4, #64 @ encoding: [0xc0,0xef,0xd8,0x01]
60 @ CHECK: vsra.s64 d10, d10, #64 @ encoding: [0x80,0xef,0x9a,0xa1]
64 @ CHECK: vsra.s64 q4, q4, #64 @ encoding: [0x80,0xef,0xd8,0x81]
78 vrsra.s64 d14, d23, #64
86 vrsra.s64 q4, q5, #64
[all …]
Dneont2-shift-encoding.s59 @ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x00]
60 vshr.s64 d16, d16, #64
67 @ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xc0,0xef,0xf0,0x00]
68 vshr.s64 q8, q8, #64
99 @ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0x70,0xef,0xa1,0x05]
100 vrshl.s64 d16, d17, d16
115 @ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0x70,0xef,0xe2,0x05]
116 vrshl.s64 q8, q9, q8
131 @ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x02]
132 vrshr.s64 d16, d16, #64
[all …]
Dneon-mov-encoding.s87 vqmovn.s64 d16, q8
93 vqmovun.s64 d16, q8
100 @ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3]
106 @ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3]
144 vmvn.s64 d1, d2
Dneont2-mov-encoding.s81 vqmovn.s64 d16, q8
87 vqmovun.s64 d16, q8
100 @ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xfa,0xff,0xa0,0x02]
106 @ CHECK: vqmovun.s64 d16, q8 @ encoding: [0xfa,0xff,0x60,0x02]
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_vert.s231 vshr.s64 d24, d24, #8
234 vshr.s64 d25, d25, #8
241 vshr.s64 d24, d24, #8
244 vshr.s64 d25, d25, #8
266 vshr.s64 d24, d24, #8
269 vshr.s64 d25, d25, #8
279 vshr.s64 d24, d24, #8
282 vshr.s64 d25, d25, #8
296 vshr.s64 d24, d24, #8
299 vshr.s64 d25, d25, #8
[all …]
Dihevc_intra_pred_luma_dc.s135 vshr.s64 d8, d8, #32
190 vshl.s64 d9, d6, d8 @(dc_val) shr by log2nt+1
197 vshl.s64 d13, d9, #1 @2*dc
480 vshr.s64 d3, d3, #40 @row 0 shift (prol) (first value to be ignored)
485 vshr.s64 d3, d3, #8 @row 1 shift (prol)
493 vshr.s64 d3, d3, #8 @row 2 shift (prol)
/external/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S118 vshr.s64 q12,q12,#26
119 vshr.s64 q13,q13,#26
127 vshr.s64 q12,q14,#25
129 vshr.s64 q13,q15,#25
135 vshr.s64 q12,q14,#26
142 vshr.s64 q13,q14,#26
144 vshr.s64 q12,q15,#25
153 vshr.s64 q13,q14,#25
155 vshr.s64 q12,q15,#26
166 vshr.s64 q0,q0,#25
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dsext-in-reg.ll7 ; CHECK: cvt.s64.s8
8 ; CHECK: cvt.s64.s8
26 ; CHECK: cvt.s64.s32
27 ; CHECK: cvt.s64.s32
44 ; CHECK: cvt.s64.s16
45 ; CHECK: cvt.s64.s16
Dmulwide.ll52 ; NOOPT: mul.lo.s64
63 ; NOOPT: mul.lo.s64
74 ; NOOPT: mul.lo.s64
85 ; NOOPT: mul.lo.s64
Dlower-aggr-copies.ll30 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd[[COUNTER]], 1
48 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd[[COUNTER]], 1
84 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd[[COUNTER]], 1
103 ; PTX: setp.eq.s64 %p[[NEQ0:[0-9]+]], %rd[[N]], 0
108 ; PTX: add.s64 %rd[[N]], %rd[[N]], -1
116 ; PTX: add.s64 %rd[[INDEX:[0-9]+]], %rd[[INDEX]], 1
Dadd-128bit.ll8 ; CHECK: add.s64
13 ; CHECK: add.s64
Dcombine-min-max.ll213 ; CHECK: max.s64
221 ; CHECK: max.s64
229 ; CHECK: min.s64
237 ; CHECK: min.s64
279 ; CHECK: min.s64
287 ; CHECK: min.s64
295 ; CHECK: max.s64
303 ; CHECK: max.s64
Dshift-parts.ll29 ; CHECK: shr.s64
32 ; CHECK: shr.s64
/external/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/
Dreassociate-geps-and-slsr.ll42 ; PTX: add.s64 [[base1:%rd[0-9]+]], [[arr]], [[i4]];
50 ; PTX: add.s64 [[base2:%rd[0-9]+]], [[base1]], [[i4]];
58 ; PTX: add.s64 [[base3:%rd[0-9]+]], [[base2]], [[i4]];
66 ; PTX: add.s64 [[base4:%rd[0-9]+]], [[base3]], [[i4]];
/external/boringssl/linux-arm/crypto/aes/
Dbsaes-armv7.S1639 vshr.s64 q6, q8, #63
1645 vshr.s64 q7, q9, #63
1651 vshr.s64 q6, q10, #63
1658 vshr.s64 q7, q11, #63
1666 vshr.s64 q6, q12, #63
1674 vshr.s64 q7, q13, #63
1682 vshr.s64 q6, q14, #63
1690 vshr.s64 q7, q15, #63
1742 vshr.s64 q7, q8, #63
1748 vshr.s64 q6, q9, #63
[all …]
/external/llvm/unittests/ADT/
DAPIntTest.cpp283 auto s64 = APInt{128, static_cast<uint64_t>(int64max), true}; in TEST()
303 EXPECT_TRUE(!s64.uge(uint64max)); in TEST()
304 EXPECT_TRUE(!s64.ugt(uint64max)); in TEST()
305 EXPECT_TRUE( s64.ule(uint64max)); in TEST()
306 EXPECT_TRUE( s64.ult(uint64max)); in TEST()
307 EXPECT_TRUE( s64.sge(int64max)); in TEST()
308 EXPECT_TRUE(!s64.sgt(int64max)); in TEST()
309 EXPECT_TRUE( s64.sle(int64max)); in TEST()
310 EXPECT_TRUE(!s64.slt(int64max)); in TEST()
311 EXPECT_TRUE( s64.sge(int64min)); in TEST()
[all …]
/external/llvm/test/CodeGen/X86/
Drd-mod-wr-eflags.ll72 %s64 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 0
74 %0 = load i64, i64* %s64, align 8
77 store i64 %dec, i64* %s64, align 8
126 %s64 = getelementptr inbounds %struct.obj2, %struct.obj2* %o, i64 0, i32 0
128 %0 = load i64, i64* %s64, align 8
131 store i64 %inc, i64* %s64, align 8
/external/compiler-rt/lib/sanitizer_common/
Dsanitizer_libc.h29 s64 internal_atoll(const char *nptr);
56 s64 internal_simple_strtoll(const char *nptr, char **endptr, int base);

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