320 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) {  in Sc()
325 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) {  in Scd()
330 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) {  in Ll()
335 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) {  in Lld()
1803 void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base,  in LoadFromOffset()
1848 void Mips64Assembler::LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base,  in LoadFpuFromOffset()
1906 void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base,  in StoreToOffset()
1943 void Mips64Assembler::StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base,  in StoreFpuToOffset()
2150 void Mips64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs,  in LoadRef()
2165 void Mips64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base,  in LoadRawPtr()
2407   Mips64ManagedRegister base = mbase.AsMips64();  in Call()  local
2418 void Mips64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) {  in Call()