91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd,  in EmitR()
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd,  in EmitRsd()
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd,  in EmitRtd()
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Addu()
187 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Daddu()
195 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Subu()
199 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Dsubu()
203 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in MulR6()
207 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in MuhR6()
211 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in DivR6()
215 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in ModR6()
219 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in DivuR6()
223 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in ModuR6()
227 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Dmul()
231 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Dmuh()
235 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Ddiv()
239 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Dmod()
243 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Ddivu()
247 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Dmodu()
251 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in And()
259 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Or()
267 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Xor()
275 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Nor()
279 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) {  in Bitswap()
283 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) {  in Dbitswap()
287 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) {  in Seb()
291 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) {  in Seh()
295 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) {  in Dsbh()
299 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) {  in Dshd()
316 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) {  in Wsbh()
340 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {  in Sll()
344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {  in Srl()
348 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) {  in Rotr()
352 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {  in Sra()
356 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Sllv()
360 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Rotrv()
364 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Srlv()
368 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Srav()
372 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsll()
376 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsrl()
380 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) {  in Drotr()
384 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsra()
388 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsll32()
392 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsrl32()
396 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) {  in Drotr32()
400 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) {  in Dsra32()
404 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Dsllv()
408 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Dsrlv()
412 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Drotrv()
416 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) {  in Dsrav()
481 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Slt()
485 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Sltu()
497 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Seleqz()
501 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) {  in Selnez()
505 void Mips64Assembler::Clz(GpuRegister rd, GpuRegister rs) {  in Clz()
509 void Mips64Assembler::Clo(GpuRegister rd, GpuRegister rs) {  in Clo()
513 void Mips64Assembler::Dclz(GpuRegister rd, GpuRegister rs) {  in Dclz()
517 void Mips64Assembler::Dclo(GpuRegister rd, GpuRegister rs) {  in Dclo()
521 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {  in Jalr()
1023 void Mips64Assembler::Move(GpuRegister rd, GpuRegister rs) {  in Move()
1027 void Mips64Assembler::Clear(GpuRegister rd) {  in Clear()
1031 void Mips64Assembler::Not(GpuRegister rd, GpuRegister rs) {  in Not()
1035 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) {  in LoadConst32()
1049 void Mips64Assembler::LoadConst64(GpuRegister rd, int64_t value) {  in LoadConst64()