Lines Matching defs:rt
91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
131 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI()
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
183 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu()
187 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
191 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu()
195 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
199 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
203 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
207 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
211 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
215 void Mips64Assembler::ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModR6()
219 void Mips64Assembler::DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivuR6()
223 void Mips64Assembler::ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in ModuR6()
227 void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmul()
231 void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmuh()
235 void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddiv()
239 void Mips64Assembler::Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmod()
243 void Mips64Assembler::Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Ddivu()
247 void Mips64Assembler::Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dmodu()
251 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And()
255 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi()
259 void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Or()
263 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori()
267 void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Xor()
271 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori()
275 void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Nor()
279 void Mips64Assembler::Bitswap(GpuRegister rd, GpuRegister rt) { in Bitswap()
283 void Mips64Assembler::Dbitswap(GpuRegister rd, GpuRegister rt) { in Dbitswap()
287 void Mips64Assembler::Seb(GpuRegister rd, GpuRegister rt) { in Seb()
291 void Mips64Assembler::Seh(GpuRegister rd, GpuRegister rt) { in Seh()
295 void Mips64Assembler::Dsbh(GpuRegister rd, GpuRegister rt) { in Dsbh()
299 void Mips64Assembler::Dshd(GpuRegister rd, GpuRegister rt) { in Dshd()
303 void Mips64Assembler::Dext(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dext()
309 void Mips64Assembler::Dinsu(GpuRegister rt, GpuRegister rs, int pos, int size) { in Dinsu()
316 void Mips64Assembler::Wsbh(GpuRegister rd, GpuRegister rt) { in Wsbh()
320 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) { in Sc()
325 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) { in Scd()
330 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) { in Ll()
335 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) { in Lld()
340 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll()
344 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl()
348 void Mips64Assembler::Rotr(GpuRegister rd, GpuRegister rt, int shamt) { in Rotr()
352 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) { in Sra()
356 void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Sllv()
360 void Mips64Assembler::Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Rotrv()
364 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv()
368 void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srav()
372 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll()
376 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl()
380 void Mips64Assembler::Drotr(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr()
384 void Mips64Assembler::Dsra(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra()
388 void Mips64Assembler::Dsll32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsll32()
392 void Mips64Assembler::Dsrl32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsrl32()
396 void Mips64Assembler::Drotr32(GpuRegister rd, GpuRegister rt, int shamt) { in Drotr32()
400 void Mips64Assembler::Dsra32(GpuRegister rd, GpuRegister rt, int shamt) { in Dsra32()
404 void Mips64Assembler::Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsllv()
408 void Mips64Assembler::Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrlv()
412 void Mips64Assembler::Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Drotrv()
416 void Mips64Assembler::Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Dsrav()
420 void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lb()
424 void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lh()
428 void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lw()
432 void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ld()
436 void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lbu()
440 void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lhu()
444 void Mips64Assembler::Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Lwu()
448 void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { in Lui()
465 void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sb()
469 void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sh()
473 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw()
477 void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sd()
481 void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Slt()
485 void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Sltu()
489 void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Slti()
493 void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sltiu()
497 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Seleqz()
501 void Mips64Assembler::Selnez(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Selnez()
546 void Mips64Assembler::Jic(GpuRegister rt, uint16_t imm16) { in Jic()
550 void Mips64Assembler::Jialc(GpuRegister rt, uint16_t imm16) { in Jialc()
554 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltc()
561 void Mips64Assembler::Bltzc(GpuRegister rt, uint16_t imm16) { in Bltzc()
566 void Mips64Assembler::Bgtzc(GpuRegister rt, uint16_t imm16) { in Bgtzc()
571 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgec()
578 void Mips64Assembler::Bgezc(GpuRegister rt, uint16_t imm16) { in Bgezc()
583 void Mips64Assembler::Blezc(GpuRegister rt, uint16_t imm16) { in Blezc()
588 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bltuc()
595 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bgeuc()
602 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beqc()
609 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Bnec()
636 GpuRegister rt, in EmitBcondc()
973 void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) { in Mfc1()
977 void Mips64Assembler::Mfhc1(GpuRegister rt, FpuRegister fs) { in Mfhc1()
981 void Mips64Assembler::Mtc1(GpuRegister rt, FpuRegister fs) { in Mtc1()
985 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) { in Mthc1()
989 void Mips64Assembler::Dmfc1(GpuRegister rt, FpuRegister fs) { in Dmfc1()
993 void Mips64Assembler::Dmtc1(GpuRegister rt, FpuRegister fs) { in Dmtc1()
1161 void Mips64Assembler::Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp) { in Daddiu64()
1747 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Bltc()
1751 void Mips64Assembler::Bltzc(GpuRegister rt, Mips64Label* label) { in Bltzc()
1755 void Mips64Assembler::Bgtzc(GpuRegister rt, Mips64Label* label) { in Bgtzc()
1759 void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Bgec()
1763 void Mips64Assembler::Bgezc(GpuRegister rt, Mips64Label* label) { in Bgezc()
1767 void Mips64Assembler::Blezc(GpuRegister rt, Mips64Label* label) { in Blezc()
1771 void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Bltuc()
1775 void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Bgeuc()
1779 void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Beqc()
1783 void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label) { in Bnec()