273     DstSub = MI->getOperand(0).getSubReg();  in isMoveInstr()
275     SrcSub = MI->getOperand(1).getSubReg();  in isMoveInstr()
278     DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),  in isMoveInstr()
281     SrcSub = MI->getOperand(2).getSubReg();  in isMoveInstr()
328       Dst = TRI.getSubReg(Dst, DstSub);  in setRegisters()
422       Dst = TRI.getSubReg(Dst, DstSub);  in isCoalescable()
427     return TRI.getSubReg(DstReg, SrcSub) == Dst;  in isCoalescable()
765         UseMI->getOperand(0).getSubReg())  in removeCopyByCommutingDef()
864     if (Op.getSubReg() == 0 || Op.isUndef())  in definesFullReg()
909   if (DstOperand.getSubReg() && !DstOperand.isUndef())  in reMaterializeTrivialDef()
926                                               DefMI->getOperand(0).getSubReg());  in reMaterializeTrivialDef()
928         NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);  in reMaterializeTrivialDef()
956     if (DefMO.getSubReg() == DstIdx) {  in reMaterializeTrivialDef()
989     unsigned NewIdx = NewMI->getOperand(0).getSubReg();  in reMaterializeTrivialDef()
1035   if (NewMI->getOperand(0).getSubReg())  in reMaterializeTrivialDef()
1140     LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());  in eliminateUndefCopy()
1840            TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));  in computeWriteLanes()
2232                   TRI->composeSubRegIndices(SubIdx, MO.getSubReg())))  in usesLanes()