248   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);  in addPhysRegDataDeps()
275         RegUse = UseSU->getInstr();  in addPhysRegDataDeps()
278         SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,  in addPhysRegDataDeps()
291   MachineInstr *MI = SU->getInstr();  in addPhysRegDeps()
311            !DefSU->getInstr()->registerDefIsDead(*Alias))) {  in addPhysRegDeps()
317             SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addPhysRegDeps()
386   MachineInstr *MI = SU->getInstr();  in addVRegDefDeps()
424         MachineInstr *Use = UseSU->getInstr();  in addVRegDefDeps()
470       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));  in addVRegDefDeps()
495   const MachineInstr *MI = SU->getInstr();  in addVRegUseDeps()
660       isGlobalMemoryObject(AA, SUb->getInstr()))  in iterateChainSucc()
667       MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {  in iterateChainSucc()
699     if (MIsNeedChainEdge(AA, MFI, DL, SU->getInstr(), (*I)->getInstr())) {  in adjustChainDeps()
701       Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0);  in adjustChainDeps()
725   if (MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {  in addChainDependency()
767     SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());  in initSUnits()
798   const MachineInstr *MI = SU->getInstr();  in collectVRegUses()
986         if (AliasChain->getInstr()->mayLoad())  in buildSchedGraph()
1348   SU->getInstr()->dump();  in dumpNode()
1360     SU->getInstr()->print(oss, /*SkipOpers=*/true);  in getGraphNodeLabel()
1416       SU->getInstr()->isTransient() ? 0 : 1;  in visitPreorder()
1427     RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;  in visitPostorderNode()