366   SUnit *PredSU = PredEdge->getSUnit();  in ReleasePred()  local
369   if (PredSU->NumSuccsLeft == 0) {  in ReleasePred()
371     PredSU->dump(this);  in ReleasePred()
376   --PredSU->NumSuccsLeft;  in ReleasePred()
381     PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency());  in ReleasePred()
386   if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {  in ReleasePred()
387     PredSU->isAvailable = true;  in ReleasePred()
389     unsigned Height = PredSU->getHeight();  in ReleasePred()
393     if (isReady(PredSU)) {  in ReleasePred()
394       AvailableQueue->push(PredSU);  in ReleasePred()
398     else if (!PredSU->isPending) {  in ReleasePred()
399       PredSU->isPending = true;  in ReleasePred()
400       PendingQueue.push_back(PredSU);  in ReleasePred()
792   SUnit *PredSU = PredEdge->getSUnit();  in CapturePred()  local
793   if (PredSU->isAvailable) {  in CapturePred()
794     PredSU->isAvailable = false;  in CapturePred()
795     if (!PredSU->isPending)  in CapturePred()
796       AvailableQueue->remove(PredSU);  in CapturePred()
799   assert(PredSU->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");  in CapturePred()
800   ++PredSU->NumSuccsLeft;  in CapturePred()
1860     SUnit *PredSU = I->getSUnit();  in CalcNodeSethiUllmanNumber()  local
1861     unsigned PredSethiUllman = CalcNodeSethiUllmanNumber(PredSU, SUNumbers);  in CalcNodeSethiUllmanNumber()
1963     SUnit *PredSU = I->getSUnit();  in HighRegPressure()  local
1966     if (PredSU->NumRegDefsLeft == 0) {  in HighRegPressure()
1969     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in HighRegPressure()
2013     SUnit *PredSU = I->getSUnit();  in RegPressureDiff()  local
2016     if (PredSU->NumRegDefsLeft == 0) {  in RegPressureDiff()
2017       if (PredSU->getNode()->isMachineOpcode())  in RegPressureDiff()
2021     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in RegPressureDiff()
2057     SUnit *PredSU = I->getSUnit();  in scheduledNode()  local
2060     if (PredSU->NumRegDefsLeft == 0) {  in scheduledNode()
2078     --PredSU->NumRegDefsLeft;  in scheduledNode()
2079     unsigned SkipRegDefs = PredSU->NumRegDefsLeft;  in scheduledNode()
2080     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);  in scheduledNode()
2139     SUnit *PredSU = I->getSUnit();  in unscheduledNode()  local
2142     if (PredSU->NumSuccsLeft != PredSU->Succs.size())  in unscheduledNode()
2144     const SDNode *PN = PredSU->getNode();  in unscheduledNode()
2238     const SUnit *PredSU = I->getSUnit();  in hasOnlyLiveInOpers()  local
2239     if (PredSU->getNode() &&  in hasOnlyLiveInOpers()
2240         PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {  in hasOnlyLiveInOpers()
2242         cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();  in hasOnlyLiveInOpers()
2312     SUnit *PredSU = I->getSUnit();  in resetVRegCycle()  local
2313     if (PredSU->isVRegCycle) {  in resetVRegCycle()
2314       assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&  in resetVRegCycle()
2845     SUnit *PredSU = nullptr;  in PrescheduleNodesWithMultipleUses()  local
2849         PredSU = II->getSUnit();  in PrescheduleNodesWithMultipleUses()
2852     assert(PredSU);  in PrescheduleNodesWithMultipleUses()
2856     if (PredSU->hasPhysRegDefs)  in PrescheduleNodesWithMultipleUses()
2859     if (PredSU->NumSuccs == 1)  in PrescheduleNodesWithMultipleUses()
2870     for (SUnit::const_succ_iterator II = PredSU->Succs.begin(),  in PrescheduleNodesWithMultipleUses()
2871          EE = PredSU->Succs.end(); II != EE; ++II) {  in PrescheduleNodesWithMultipleUses()
2890                  << " next to PredSU #" << PredSU->NodeNum  in PrescheduleNodesWithMultipleUses()
2892     for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {  in PrescheduleNodesWithMultipleUses()
2893       SDep Edge = PredSU->Succs[i];  in PrescheduleNodesWithMultipleUses()
2897         Edge.setSUnit(PredSU);  in PrescheduleNodesWithMultipleUses()