Lines Matching refs:SU
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
209 SU->removePred(D); in RemovePred()
213 bool isReady(SUnit *SU) { in isReady() argument
215 AvailableQueue->isReady(SU); in isReady()
218 void ReleasePred(SUnit *SU, const SDep *PredEdge);
219 void ReleasePredecessors(SUnit *SU);
222 void AdvancePastStalls(SUnit *SU);
223 void EmitNode(SUnit *SU);
365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred() argument
381 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); in ReleasePred()
525 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors() argument
527 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
529 ReleasePred(SU, &*I); in ReleasePredecessors()
536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) && in ReleasePredecessors()
541 LiveRegGens[I->getReg()] = SU; in ReleasePredecessors()
551 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) in ReleasePredecessors()
559 CallSeqEndForStart[Def] = SU; in ReleasePredecessors()
563 LiveRegGens[CallResource] = SU; in ReleasePredecessors()
622 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls() argument
633 unsigned ReadyCycle = SU->getHeight(); in AdvancePastStalls()
644 if (SU->isCall) in AdvancePastStalls()
652 HazardRec->getHazardType(SU, -Stalls); in AdvancePastStalls()
664 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode() argument
669 if (!SU->getNode()) in EmitNode()
672 switch (SU->getNode()->getOpcode()) { in EmitNode()
674 assert(SU->getNode()->isMachineOpcode() && in EmitNode()
692 if (SU->isCall) { in EmitNode()
698 HazardRec->EmitInstruction(SU); in EmitNode()
701 static void resetVRegCycle(SUnit *SU);
706 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp() argument
708 DEBUG(SU->dump(this)); in ScheduleNodeBottomUp()
711 if (CurCycle < SU->getHeight()) in ScheduleNodeBottomUp()
712 DEBUG(dbgs() << " Height [" << SU->getHeight() in ScheduleNodeBottomUp()
720 SU->setHeightToAtLeast(CurCycle); in ScheduleNodeBottomUp()
723 EmitNode(SU); in ScheduleNodeBottomUp()
725 Sequence.push_back(SU); in ScheduleNodeBottomUp()
727 AvailableQueue->scheduledNode(SU); in ScheduleNodeBottomUp()
737 ReleasePredecessors(SU); in ScheduleNodeBottomUp()
740 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ScheduleNodeBottomUp()
743 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] == SU) { in ScheduleNodeBottomUp()
754 if (LiveRegDefs[CallResource] == SU) in ScheduleNodeBottomUp()
755 for (const SDNode *SUNode = SU->getNode(); SUNode; in ScheduleNodeBottomUp()
767 resetVRegCycle(SU); in ScheduleNodeBottomUp()
769 SU->isScheduled = true; in ScheduleNodeBottomUp()
780 if (SU->getNode() && SU->getNode()->isMachineOpcode()) in ScheduleNodeBottomUp()
805 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp() argument
806 DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "); in UnscheduleNodeBottomUp()
807 DEBUG(SU->dump(this)); in UnscheduleNodeBottomUp()
809 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in UnscheduleNodeBottomUp()
812 if (I->isAssignedRegDep() && SU == LiveRegGens[I->getReg()]){ in UnscheduleNodeBottomUp()
826 for (const SDNode *SUNode = SU->getNode(); SUNode; in UnscheduleNodeBottomUp()
831 LiveRegDefs[CallResource] = SU; in UnscheduleNodeBottomUp()
832 LiveRegGens[CallResource] = CallSeqEndForStart[SU]; in UnscheduleNodeBottomUp()
838 if (LiveRegGens[CallResource] == SU) in UnscheduleNodeBottomUp()
839 for (const SDNode *SUNode = SU->getNode(); SUNode; in UnscheduleNodeBottomUp()
851 for (auto &Succ : SU->Succs) { in UnscheduleNodeBottomUp()
858 LiveRegDefs[Reg] = SU; in UnscheduleNodeBottomUp()
865 for (auto &Succ2 : SU->Succs) { in UnscheduleNodeBottomUp()
873 if (SU->getHeight() < MinAvailableCycle) in UnscheduleNodeBottomUp()
874 MinAvailableCycle = SU->getHeight(); in UnscheduleNodeBottomUp()
876 SU->setHeightDirty(); in UnscheduleNodeBottomUp()
877 SU->isScheduled = false; in UnscheduleNodeBottomUp()
878 SU->isAvailable = true; in UnscheduleNodeBottomUp()
881 SU->isPending = true; in UnscheduleNodeBottomUp()
882 PendingQueue.push_back(SU); in UnscheduleNodeBottomUp()
885 AvailableQueue->push(SU); in UnscheduleNodeBottomUp()
887 AvailableQueue->unscheduledNode(SU); in UnscheduleNodeBottomUp()
903 SUnit *SU = *I; in RestoreHazardCheckerBottomUp() local
904 for (; SU->getHeight() > HazardCycle; ++HazardCycle) { in RestoreHazardCheckerBottomUp()
907 EmitNode(SU); in RestoreHazardCheckerBottomUp()
913 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp() argument
926 assert(!SU->isSucc(OldSU) && "Something is wrong!"); in BacktrackBottomUp()
935 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf() argument
936 for (const SDNode *SUNode = SU->getNode(); SUNode; in isOperandOf()
946 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors() argument
947 SDNode *N = SU->getNode(); in CopyAndMoveSuccessors()
951 if (SU->getNode()->getGluedNode()) in CopyAndMoveSuccessors()
979 DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"); in CopyAndMoveSuccessors()
985 unsigned OldNumVals = SU->getNode()->getNumValues(); in CopyAndMoveSuccessors()
987 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i)); in CopyAndMoveSuccessors()
988 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals-1), in CopyAndMoveSuccessors()
1030 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CopyAndMoveSuccessors()
1039 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in CopyAndMoveSuccessors()
1050 RemovePred(SU, Pred); in CopyAndMoveSuccessors()
1056 RemovePred(SU, Pred); in CopyAndMoveSuccessors()
1062 RemovePred(SU, Pred); in CopyAndMoveSuccessors()
1068 D.setSUnit(SU); in CopyAndMoveSuccessors()
1080 D.setSUnit(SU); in CopyAndMoveSuccessors()
1104 SU = NewSU; in CopyAndMoveSuccessors()
1107 DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); in CopyAndMoveSuccessors()
1108 NewSU = CreateClone(SU); in CopyAndMoveSuccessors()
1111 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CopyAndMoveSuccessors()
1119 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in CopyAndMoveSuccessors()
1128 D.setSUnit(SU); in CopyAndMoveSuccessors()
1135 AvailableQueue->updateNode(SU); in CopyAndMoveSuccessors()
1144 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs() argument
1159 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in InsertCopiesAndMoveSuccs()
1180 SDep FromDep(SU, SDep::Data, Reg); in InsertCopiesAndMoveSuccs()
1181 FromDep.setLatency(SU->Latency); in InsertCopiesAndMoveSuccs()
1187 AvailableQueue->updateNode(SU); in InsertCopiesAndMoveSuccs()
1220 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, in CheckForLiveRegDef() argument
1231 if (LiveRegDefs[*AliasI] == SU) continue; in CheckForLiveRegDef()
1242 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1249 if (LiveRegDefs[i] == SU) continue; in CheckForLiveRegDefMasked()
1269 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp() argument
1278 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in DelayForLiveRegsBottomUp()
1280 if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU) in DelayForLiveRegsBottomUp()
1285 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) { in DelayForLiveRegsBottomUp()
1305 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); in DelayForLiveRegsBottomUp()
1331 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
1339 CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); in DelayForLiveRegsBottomUp()
1348 SUnit *SU = Interferences[i-1]; in releaseInterferences() local
1349 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU); in releaseInterferences()
1355 SU->isPending = false; in releaseInterferences()
1359 if (SU->isAvailable && !SU->NodeQueueId) { in releaseInterferences()
1360 DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n'); in releaseInterferences()
1361 AvailableQueue->push(SU); in releaseInterferences()
1520 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp() local
1522 AdvancePastStalls(SU); in ListScheduleBottomUp()
1524 ScheduleNodeBottomUp(SU); in ListScheduleBottomUp()
1552 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1608 bool isReady(SUnit *SU, unsigned CurCycle) const;
1625 bool isReady(SUnit *SU, unsigned CurCycle) const;
1690 void addNode(const SUnit *SU) override;
1692 void updateNode(const SUnit *SU) override;
1700 unsigned getNodePriority(const SUnit *SU) const;
1702 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1703 if (!SU->getNode()) return 0; in getNodeOrdering()
1705 return SU->getNode()->getIROrder(); in getNodeOrdering()
1716 void remove(SUnit *SU) override { in remove() argument
1718 assert(SU->NodeQueueId != 0 && "Not in queue!"); in remove()
1720 SU); in remove()
1724 SU->NodeQueueId = 0; in remove()
1731 bool HighRegPressure(const SUnit *SU) const;
1733 bool MayReduceRegPressure(SUnit *SU) const;
1735 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1737 void scheduledNode(SUnit *SU) override;
1739 void unscheduledNode(SUnit *SU) override;
1742 bool canClobber(const SUnit *SU, const SUnit *Op);
1809 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump() local
1810 dbgs() << "Height " << SU->getHeight() << ": "; in dump()
1811 SU->dump(DAG); in dump()
1851 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
1852 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
1857 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in CalcNodeSethiUllmanNumber()
1886 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode() argument
1890 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); in addNode()
1893 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode() argument
1894 SethiUllmanNumbers[SU->NodeNum] = 0; in updateNode()
1895 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); in updateNode()
1900 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
1901 assert(SU->NodeNum < SethiUllmanNumbers.size()); in getNodePriority()
1902 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; in getNodePriority()
1913 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
1920 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
1925 return SethiUllmanNumbers[SU->NodeNum]; in getNodePriority()
1927 unsigned Priority = SethiUllmanNumbers[SU->NodeNum]; in getNodePriority()
1928 if (SU->isCallOp) { in getNodePriority()
1930 int NP = (int)Priority - SU->getNode()->getNumValues(); in getNodePriority()
1955 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
1959 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in HighRegPressure()
1981 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
1982 const SDNode *N = SU->getNode(); in MayReduceRegPressure()
1984 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2006 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff() argument
2009 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in RegPressureDiff()
2029 const SDNode *N = SU->getNode(); in RegPressureDiff()
2031 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2046 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode() argument
2050 if (!SU->getNode()) in scheduledNode()
2053 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in scheduledNode()
2095 int SkipRegDefs = (int)SU->NumRegDefsLeft; in scheduledNode()
2096 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG); in scheduledNode()
2105 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") has too many regdefs\n"); in scheduledNode()
2115 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode() argument
2119 const SDNode *N = SU->getNode(); in unscheduledNode()
2135 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in unscheduledNode()
2180 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2202 static unsigned closestSucc(const SUnit *SU) { in closestSucc() argument
2204 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in closestSucc()
2221 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches() argument
2223 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in calcMaxScratches()
2233 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers() argument
2235 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in hasOnlyLiveInOpers()
2256 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses() argument
2258 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in hasOnlyLiveOutUses()
2285 static void initVRegCycle(SUnit *SU) { in initVRegCycle() argument
2289 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU)) in initVRegCycle()
2292 DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); in initVRegCycle()
2294 SU->isVRegCycle = true; in initVRegCycle()
2296 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in initVRegCycle()
2305 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle() argument
2306 if (!SU->isVRegCycle) in resetVRegCycle()
2309 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in resetVRegCycle()
2323 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse() argument
2325 if (SU->isVRegCycle) in hasVRegCycleUse()
2328 for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end(); in hasVRegCycleUse()
2333 DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); in hasVRegCycleUse()
2343 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall() argument
2345 if (SPQ->getHazardRec()->getHazardType(SU, 0) in BUHasStall()
2535 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady() argument
2538 if (SPQ->MayReduceRegPressure(SU)) return true; in isReady()
2540 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false; in isReady()
2542 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay) in isReady()
2582 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady() argument
2583 if (SU->getHeight() > CurCycle) return false; in isReady()
2585 if (SPQ->getHazardRec()->getHazardType(SU, 0) in isReady()
2592 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing() argument
2593 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; in canEnableCoalescing()
2606 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2698 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber() argument
2699 if (SU->isTwoAddress) { in canClobber()
2700 unsigned Opc = SU->getNode()->getMachineOpcode(); in canClobber()
2706 SDNode *DU = SU->getNode()->getOperand(i).getNode(); in canClobber()
2719 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse() argument
2724 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2725 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse()
2729 for (SUnit::const_succ_iterator SI = SU->Succs.begin(), SE = SU->Succs.end(); in canClobberReachingPhysRegUse()
2756 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs() argument
2763 for (const SDNode *SUNode = SU->getNode(); SUNode; in canClobberPhysRegDefs()
2827 SUnit *SU = &(*SUnits)[i]; in PrescheduleNodesWithMultipleUses() local
2831 if (SU->NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2834 if (SU->NumPreds != 1) in PrescheduleNodesWithMultipleUses()
2838 if (SDNode *N = SU->getNode()) in PrescheduleNodesWithMultipleUses()
2846 for (SUnit::const_pred_iterator II = SU->Preds.begin(), in PrescheduleNodesWithMultipleUses()
2847 EE = SU->Preds.end(); II != EE; ++II) in PrescheduleNodesWithMultipleUses()
2863 if (SDNode *N = SU->getNode()) in PrescheduleNodesWithMultipleUses()
2873 if (PredSuccSU == SU) continue; in PrescheduleNodesWithMultipleUses()
2879 if (SU->hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs) in PrescheduleNodesWithMultipleUses()
2880 if (canClobberPhysRegDefs(PredSuccSU, SU, TII, TRI)) in PrescheduleNodesWithMultipleUses()
2883 if (scheduleDAG->IsReachable(SU, PredSuccSU)) in PrescheduleNodesWithMultipleUses()
2889 DEBUG(dbgs() << " Prescheduling SU #" << SU->NodeNum in PrescheduleNodesWithMultipleUses()
2896 if (SuccSU != SU) { in PrescheduleNodesWithMultipleUses()
2899 scheduleDAG->AddPred(SU, Edge); in PrescheduleNodesWithMultipleUses()
2900 Edge.setSUnit(SU); in PrescheduleNodesWithMultipleUses()
2918 SUnit *SU = &(*SUnits)[i]; in AddPseudoTwoAddrDeps() local
2919 if (!SU->isTwoAddress) in AddPseudoTwoAddrDeps()
2922 SDNode *Node = SU->getNode(); in AddPseudoTwoAddrDeps()
2923 if (!Node || !Node->isMachineOpcode() || SU->getNode()->getGluedNode()) in AddPseudoTwoAddrDeps()
2926 bool isLiveOut = hasOnlyLiveOutUses(SU); in AddPseudoTwoAddrDeps()
2934 SDNode *DU = SU->getNode()->getOperand(j).getNode(); in AddPseudoTwoAddrDeps()
2943 if (SuccSU == SU) in AddPseudoTwoAddrDeps()
2947 if (SuccSU->getHeight() < SU->getHeight() && in AddPseudoTwoAddrDeps()
2948 (SU->getHeight() - SuccSU->getHeight()) > 1) in AddPseudoTwoAddrDeps()
2964 if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) { in AddPseudoTwoAddrDeps()
2965 if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) in AddPseudoTwoAddrDeps()
2975 if (!canClobberReachingPhysRegUse(SuccSU, SU, scheduleDAG, TII, TRI) && in AddPseudoTwoAddrDeps()
2978 (!SU->isCommutable && SuccSU->isCommutable)) && in AddPseudoTwoAddrDeps()
2979 !scheduleDAG->IsReachable(SuccSU, SU)) { in AddPseudoTwoAddrDeps()
2981 << SU->NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); in AddPseudoTwoAddrDeps()
2982 scheduleDAG->AddPred(SU, SDep(SuccSU, SDep::Artificial)); in AddPseudoTwoAddrDeps()