Lines Matching refs:Op0
194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, in emitAdd_ri_() argument
1490 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm); in emitAdd_ri_()
1492 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm); in emitAdd_ri_()
1501 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true); in emitAdd_ri_()
2063 const Value *Op0 = I->getOperand(0); in selectStore() local
2067 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) || in selectStore()
2074 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) { in selectStore()
2077 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) { in selectStore()
2085 SrcReg = getRegForValue(Op0); in selectStore()
3835 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitMul_rr() argument
3851 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill, in emitMul_rr()
3855 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitSMULL_rr() argument
3861 Op0, Op0IsKill, Op1, Op1IsKill, in emitSMULL_rr()
3865 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitUMULL_rr() argument
3871 Op0, Op0IsKill, Op1, Op1IsKill, in emitUMULL_rr()
3901 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
3925 .addReg(Op0, getKillRegState(Op0IsKill)); in emitLSL_ri()
3928 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
3973 .addReg(Op0, getKillRegState(Op0IsKill)) in emitLSL_ri()
3975 Op0 = TmpReg; in emitLSL_ri()
3978 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSL_ri()
4008 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4032 .addReg(Op0, getKillRegState(Op0IsKill)); in emitLSR_ri()
4035 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4073 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4074 if (!Op0) in emitLSR_ri()
4094 .addReg(Op0, getKillRegState(Op0IsKill)) in emitLSR_ri()
4096 Op0 = TmpReg; in emitLSR_ri()
4099 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSR_ri()
4129 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4153 .addReg(Op0, getKillRegState(Op0IsKill)); in emitASR_ri()
4156 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4203 .addReg(Op0, getKillRegState(Op0IsKill)) in emitASR_ri()
4205 Op0 = TmpReg; in emitASR_ri()
4208 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitASR_ri()
4559 const Value *Op0 = I->getOperand(0); in selectShift() local
4560 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) { in selectShift()
4566 Op0 = ZExt->getOperand(0); in selectShift()
4569 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) { in selectShift()
4575 Op0 = SExt->getOperand(0); in selectShift()
4580 unsigned Op0Reg = getRegForValue(Op0); in selectShift()
4583 bool Op0IsKill = hasTrivialKill(Op0); in selectShift()