Lines Matching refs:ISD
36 ISD::ArgFlagsTy ArgFlags, CCState &State) { in allocateStack()
68 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
69 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
74 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in AMDGPUTargetLowering()
80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
85 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
86 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
87 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
88 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
89 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
90 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
91 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
95 setOperationAction(ISD::FROUND, MVT::f32, Custom); in AMDGPUTargetLowering()
96 setOperationAction(ISD::FROUND, MVT::f64, Custom); in AMDGPUTargetLowering()
98 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering()
99 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering()
103 setOperationAction(ISD::FMAD, MVT::f32, Legal); in AMDGPUTargetLowering()
106 setOperationAction(ISD::FSUB, MVT::f64, Expand); in AMDGPUTargetLowering()
110 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
111 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
113 setOperationAction(ISD::STORE, MVT::v2f32, Promote); in AMDGPUTargetLowering()
114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
116 setOperationAction(ISD::STORE, MVT::v4f32, Promote); in AMDGPUTargetLowering()
117 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
119 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
120 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
122 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
125 setOperationAction(ISD::STORE, MVT::f64, Promote); in AMDGPUTargetLowering()
126 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64); in AMDGPUTargetLowering()
128 setOperationAction(ISD::STORE, MVT::v2f64, Promote); in AMDGPUTargetLowering()
129 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64); in AMDGPUTargetLowering()
133 setOperationAction(ISD::STORE, MVT::v4i32, Custom); in AMDGPUTargetLowering()
150 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
151 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
153 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
156 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
157 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
159 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
160 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
162 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
165 setOperationAction(ISD::LOAD, MVT::f64, Promote); in AMDGPUTargetLowering()
166 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64); in AMDGPUTargetLowering()
168 setOperationAction(ISD::LOAD, MVT::v2f64, Promote); in AMDGPUTargetLowering()
169 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64); in AMDGPUTargetLowering()
171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
175 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
186 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
191 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
193 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
194 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
195 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
196 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
198 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
200 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
201 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
202 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
205 setOperationAction(ISD::BR_CC, MVT::i1, Expand); in AMDGPUTargetLowering()
208 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
209 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in AMDGPUTargetLowering()
210 setOperationAction(ISD::FRINT, MVT::f64, Custom); in AMDGPUTargetLowering()
211 setOperationAction(ISD::FFLOOR, MVT::f64, Custom); in AMDGPUTargetLowering()
216 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in AMDGPUTargetLowering()
217 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in AMDGPUTargetLowering()
220 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in AMDGPUTargetLowering()
222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in AMDGPUTargetLowering()
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand); in AMDGPUTargetLowering()
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand); in AMDGPUTargetLowering()
225 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
227 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in AMDGPUTargetLowering()
228 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand); in AMDGPUTargetLowering()
229 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand); in AMDGPUTargetLowering()
230 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand); in AMDGPUTargetLowering()
242 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
243 setOperationAction(ISD::SDIV, VT, Expand); in AMDGPUTargetLowering()
246 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
247 setOperationAction(ISD::UDIVREM, VT, Custom); in AMDGPUTargetLowering()
250 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in AMDGPUTargetLowering()
251 setOperationAction(ISD::UMUL_LOHI, VT, Expand); in AMDGPUTargetLowering()
253 setOperationAction(ISD::BSWAP, VT, Expand); in AMDGPUTargetLowering()
254 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering()
255 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
259 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in AMDGPUTargetLowering()
262 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in AMDGPUTargetLowering()
265 setOperationAction(ISD::ROTL, MVT::i32, Expand); in AMDGPUTargetLowering()
266 setOperationAction(ISD::ROTL, MVT::i64, Expand); in AMDGPUTargetLowering()
267 setOperationAction(ISD::ROTR, MVT::i64, Expand); in AMDGPUTargetLowering()
269 setOperationAction(ISD::MUL, MVT::i64, Expand); in AMDGPUTargetLowering()
270 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
271 setOperationAction(ISD::MULHS, MVT::i64, Expand); in AMDGPUTargetLowering()
272 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
273 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
274 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in AMDGPUTargetLowering()
278 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
280 setOperationAction(ISD::SMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
281 setOperationAction(ISD::UMIN, MVT::i32, Legal); in AMDGPUTargetLowering()
282 setOperationAction(ISD::SMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
283 setOperationAction(ISD::UMAX, MVT::i32, Legal); in AMDGPUTargetLowering()
286 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in AMDGPUTargetLowering()
289 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in AMDGPUTargetLowering()
297 setOperationAction(ISD::ADD, VT, Expand); in AMDGPUTargetLowering()
298 setOperationAction(ISD::AND, VT, Expand); in AMDGPUTargetLowering()
299 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
300 setOperationAction(ISD::FP_TO_UINT, VT, Expand); in AMDGPUTargetLowering()
301 setOperationAction(ISD::MUL, VT, Expand); in AMDGPUTargetLowering()
302 setOperationAction(ISD::OR, VT, Expand); in AMDGPUTargetLowering()
303 setOperationAction(ISD::SHL, VT, Expand); in AMDGPUTargetLowering()
304 setOperationAction(ISD::SRA, VT, Expand); in AMDGPUTargetLowering()
305 setOperationAction(ISD::SRL, VT, Expand); in AMDGPUTargetLowering()
306 setOperationAction(ISD::ROTL, VT, Expand); in AMDGPUTargetLowering()
307 setOperationAction(ISD::ROTR, VT, Expand); in AMDGPUTargetLowering()
308 setOperationAction(ISD::SUB, VT, Expand); in AMDGPUTargetLowering()
309 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
310 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
311 setOperationAction(ISD::SDIV, VT, Expand); in AMDGPUTargetLowering()
312 setOperationAction(ISD::UDIV, VT, Expand); in AMDGPUTargetLowering()
313 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
314 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
315 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in AMDGPUTargetLowering()
316 setOperationAction(ISD::UMUL_LOHI, VT, Expand); in AMDGPUTargetLowering()
317 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
318 setOperationAction(ISD::UDIVREM, VT, Expand); in AMDGPUTargetLowering()
319 setOperationAction(ISD::ADDC, VT, Expand); in AMDGPUTargetLowering()
320 setOperationAction(ISD::SUBC, VT, Expand); in AMDGPUTargetLowering()
321 setOperationAction(ISD::ADDE, VT, Expand); in AMDGPUTargetLowering()
322 setOperationAction(ISD::SUBE, VT, Expand); in AMDGPUTargetLowering()
323 setOperationAction(ISD::SELECT, VT, Expand); in AMDGPUTargetLowering()
324 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
325 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
326 setOperationAction(ISD::XOR, VT, Expand); in AMDGPUTargetLowering()
327 setOperationAction(ISD::BSWAP, VT, Expand); in AMDGPUTargetLowering()
328 setOperationAction(ISD::CTPOP, VT, Expand); in AMDGPUTargetLowering()
329 setOperationAction(ISD::CTTZ, VT, Expand); in AMDGPUTargetLowering()
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); in AMDGPUTargetLowering()
331 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
332 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); in AMDGPUTargetLowering()
333 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
341 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
342 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
343 setOperationAction(ISD::FMAXNUM, VT, Expand); in AMDGPUTargetLowering()
344 setOperationAction(ISD::FADD, VT, Expand); in AMDGPUTargetLowering()
345 setOperationAction(ISD::FCEIL, VT, Expand); in AMDGPUTargetLowering()
346 setOperationAction(ISD::FCOS, VT, Expand); in AMDGPUTargetLowering()
347 setOperationAction(ISD::FDIV, VT, Expand); in AMDGPUTargetLowering()
348 setOperationAction(ISD::FEXP2, VT, Expand); in AMDGPUTargetLowering()
349 setOperationAction(ISD::FLOG2, VT, Expand); in AMDGPUTargetLowering()
350 setOperationAction(ISD::FREM, VT, Expand); in AMDGPUTargetLowering()
351 setOperationAction(ISD::FPOW, VT, Expand); in AMDGPUTargetLowering()
352 setOperationAction(ISD::FFLOOR, VT, Expand); in AMDGPUTargetLowering()
353 setOperationAction(ISD::FTRUNC, VT, Expand); in AMDGPUTargetLowering()
354 setOperationAction(ISD::FMUL, VT, Expand); in AMDGPUTargetLowering()
355 setOperationAction(ISD::FMA, VT, Expand); in AMDGPUTargetLowering()
356 setOperationAction(ISD::FRINT, VT, Expand); in AMDGPUTargetLowering()
357 setOperationAction(ISD::FNEARBYINT, VT, Expand); in AMDGPUTargetLowering()
358 setOperationAction(ISD::FSQRT, VT, Expand); in AMDGPUTargetLowering()
359 setOperationAction(ISD::FSIN, VT, Expand); in AMDGPUTargetLowering()
360 setOperationAction(ISD::FSUB, VT, Expand); in AMDGPUTargetLowering()
361 setOperationAction(ISD::FNEG, VT, Expand); in AMDGPUTargetLowering()
362 setOperationAction(ISD::SELECT, VT, Expand); in AMDGPUTargetLowering()
363 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
364 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
365 setOperationAction(ISD::FCOPYSIGN, VT, Expand); in AMDGPUTargetLowering()
366 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
369 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom); in AMDGPUTargetLowering()
370 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom); in AMDGPUTargetLowering()
372 setTargetDAGCombine(ISD::SHL); in AMDGPUTargetLowering()
373 setTargetDAGCombine(ISD::MUL); in AMDGPUTargetLowering()
374 setTargetDAGCombine(ISD::SELECT); in AMDGPUTargetLowering()
375 setTargetDAGCombine(ISD::SELECT_CC); in AMDGPUTargetLowering()
376 setTargetDAGCombine(ISD::STORE); in AMDGPUTargetLowering()
378 setTargetDAGCombine(ISD::FADD); in AMDGPUTargetLowering()
379 setTargetDAGCombine(ISD::FSUB); in AMDGPUTargetLowering()
439 ISD::LoadExtType, in shouldReduceLoadWidth()
563 const SmallVectorImpl<ISD::InputArg> &Ins) const { in AnalyzeFormalArguments()
572 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
620 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
621 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
622 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
623 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
624 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
625 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
626 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
627 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
628 case ISD::FRINT: return LowerFRINT(Op, DAG); in LowerOperation()
629 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
630 case ISD::FROUND: return LowerFROUND(Op, DAG); in LowerOperation()
631 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
632 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
633 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
634 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
635 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); in LowerOperation()
636 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerOperation()
645 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
653 case ISD::LOAD: { in ReplaceNodeResults()
665 case ISD::STORE: { in ReplaceNodeResults()
719 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
725 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
743 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
749 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
830 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD) in LowerGlobalAddress()
862 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerCONCAT_VECTORS()
874 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerEXTRACT_SUBVECTOR()
963 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
965 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp, in LowerINTRINSIC_WO_CHAIN()
976 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
979 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
982 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
985 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
1044 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1047 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1049 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1051 return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
1060 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), in LowerIntrinsicIABS()
1063 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1)); in LowerIntrinsicIABS()
1073 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, in LowerIntrinsicLRP()
1076 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, in LowerIntrinsicLRP()
1078 return DAG.getNode(ISD::FADD, DL, VT, in LowerIntrinsicLRP()
1079 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), in LowerIntrinsicLRP()
1099 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in CombineFMinMaxLegacy()
1101 case ISD::SETOEQ: in CombineFMinMaxLegacy()
1102 case ISD::SETONE: in CombineFMinMaxLegacy()
1103 case ISD::SETUNE: in CombineFMinMaxLegacy()
1104 case ISD::SETNE: in CombineFMinMaxLegacy()
1105 case ISD::SETUEQ: in CombineFMinMaxLegacy()
1106 case ISD::SETEQ: in CombineFMinMaxLegacy()
1107 case ISD::SETFALSE: in CombineFMinMaxLegacy()
1108 case ISD::SETFALSE2: in CombineFMinMaxLegacy()
1109 case ISD::SETTRUE: in CombineFMinMaxLegacy()
1110 case ISD::SETTRUE2: in CombineFMinMaxLegacy()
1111 case ISD::SETUO: in CombineFMinMaxLegacy()
1112 case ISD::SETO: in CombineFMinMaxLegacy()
1114 case ISD::SETULE: in CombineFMinMaxLegacy()
1115 case ISD::SETULT: { in CombineFMinMaxLegacy()
1120 case ISD::SETOLE: in CombineFMinMaxLegacy()
1121 case ISD::SETOLT: in CombineFMinMaxLegacy()
1122 case ISD::SETLE: in CombineFMinMaxLegacy()
1123 case ISD::SETLT: { in CombineFMinMaxLegacy()
1139 case ISD::SETUGE: in CombineFMinMaxLegacy()
1140 case ISD::SETUGT: { in CombineFMinMaxLegacy()
1145 case ISD::SETGT: in CombineFMinMaxLegacy()
1146 case ISD::SETGE: in CombineFMinMaxLegacy()
1147 case ISD::SETOGE: in CombineFMinMaxLegacy()
1148 case ISD::SETOGT: { in CombineFMinMaxLegacy()
1157 case ISD::SETCC_INVALID: in CombineFMinMaxLegacy()
1182 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(), in ScalarizeVectorLoad()
1196 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads), in ScalarizeVectorLoad()
1197 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains) in ScalarizeVectorLoad()
1239 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in SplitVectorLoad()
1250 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad), in SplitVectorLoad()
1251 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, in SplitVectorLoad()
1286 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value, in MergeVectorStore()
1289 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg in MergeVectorStore()
1292 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift); in MergeVectorStore()
1297 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt); in MergeVectorStore()
1331 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, in ScalarizeVectorStore()
1336 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset); in ScalarizeVectorStore()
1345 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains); in ScalarizeVectorStore()
1373 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in SplitVectorStore()
1399 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore); in SplitVectorStore()
1406 ISD::LoadExtType ExtType = Load->getExtensionType(); in LowerLOAD()
1410 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) { in LowerLOAD()
1419 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
1423 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD), in LowerLOAD()
1432 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
1439 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(), in LowerLOAD()
1448 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in LowerLOAD()
1453 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerLOAD()
1457 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt); in LowerLOAD()
1463 if (ExtType == ISD::SEXTLOAD) { in LowerLOAD()
1467 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode), in LowerLOAD()
1508 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr, in LowerSTORE()
1514 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr, in LowerSTORE()
1517 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in LowerSTORE()
1520 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in LowerSTORE()
1525 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in LowerSTORE()
1528 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, in LowerSTORE()
1531 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask, in LowerSTORE()
1533 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in LowerSTORE()
1535 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in LowerSTORE()
1554 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1555 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
1569 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS); in LowerDIVREM24()
1572 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
1576 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
1598 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT, in LowerDIVREM24()
1602 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1605 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
1608 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT, in LowerDIVREM24()
1609 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa); in LowerDIVREM24()
1615 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1618 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
1623 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
1626 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT)); in LowerDIVREM24()
1632 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24()
1635 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
1636 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); in LowerDIVREM24()
1659 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero); in LowerUDIVREM64()
1660 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one); in LowerUDIVREM64()
1663 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero); in LowerUDIVREM64()
1664 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one); in LowerUDIVREM64()
1670 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerUDIVREM64()
1673 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero); in LowerUDIVREM64()
1674 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero); in LowerUDIVREM64()
1681 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
1682 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
1684 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1685 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero); in LowerUDIVREM64()
1687 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ); in LowerUDIVREM64()
1696 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS); in LowerUDIVREM64()
1697 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one); in LowerUDIVREM64()
1698 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); in LowerUDIVREM64()
1701 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
1703 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); in LowerUDIVREM64()
1706 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE); in LowerUDIVREM64()
1708 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT); in LowerUDIVREM64()
1711 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); in LowerUDIVREM64()
1712 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1715 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi); in LowerUDIVREM64()
1749 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den); in LowerUDIVREM()
1752 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1755 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), in LowerUDIVREM()
1761 ISD::SETEQ); in LowerUDIVREM()
1764 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1767 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); in LowerUDIVREM()
1770 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); in LowerUDIVREM()
1775 ISD::SETEQ); in LowerUDIVREM()
1777 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
1780 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den); in LowerUDIVREM()
1783 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder); in LowerUDIVREM()
1789 ISD::SETUGE); in LowerUDIVREM()
1795 ISD::SETUGE); in LowerUDIVREM()
1797 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM()
1803 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient, in LowerUDIVREM()
1807 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, in LowerUDIVREM()
1812 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
1816 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
1821 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den); in LowerUDIVREM()
1824 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den); in LowerUDIVREM()
1828 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
1832 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
1862 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero); in LowerSDIVREM()
1863 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero); in LowerSDIVREM()
1864 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
1867 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)), in LowerSDIVREM()
1868 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1)) in LowerSDIVREM()
1873 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1874 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); in LowerSDIVREM()
1875 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM()
1878 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign); in LowerSDIVREM()
1879 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM()
1881 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign); in LowerSDIVREM()
1882 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
1884 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
1887 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
1888 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign); in LowerSDIVREM()
1890 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); in LowerSDIVREM()
1891 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign); in LowerSDIVREM()
1909 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y); in LowerFREM()
1910 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); in LowerFREM()
1911 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y); in LowerFREM()
1913 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); in LowerFREM()
1924 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
1932 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
1933 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFCEIL()
1934 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFCEIL()
1936 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero); in LowerFCEIL()
1938 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFCEIL()
1949 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart, in extractF64Exponent()
1964 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
1968 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
1976 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask); in LowerFTRUNC()
1979 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in LowerFTRUNC()
1981 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
1983 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src); in LowerFTRUNC()
1987 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
1989 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC()
1996 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFTRUNC()
1997 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFTRUNC()
1999 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
2000 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); in LowerFTRUNC()
2002 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); in LowerFTRUNC()
2013 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src); in LowerFRINT()
2017 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); in LowerFRINT()
2018 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); in LowerFRINT()
2020 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
2027 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
2036 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0)); in LowerFNEARBYINT()
2044 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X); in LowerFROUND32()
2048 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T); in LowerFROUND32()
2050 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff); in LowerFROUND32()
2056 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X); in LowerFROUND32()
2061 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND32()
2063 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero); in LowerFROUND32()
2065 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel); in LowerFROUND32()
2072 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X); in LowerFROUND64()
2081 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X); in LowerFROUND64()
2083 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One); in LowerFROUND64()
2090 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp); in LowerFROUND64()
2091 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64, in LowerFROUND64()
2096 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M); in LowerFROUND64()
2099 ISD::SETNE); in LowerFROUND64()
2101 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, in LowerFROUND64()
2103 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2); in LowerFROUND64()
2105 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64)); in LowerFROUND64()
2106 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K); in LowerFROUND64()
2108 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); in LowerFROUND64()
2109 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT); in LowerFROUND64()
2110 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ); in LowerFROUND64()
2112 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64, in LowerFROUND64()
2117 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X); in LowerFROUND64()
2119 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K); in LowerFROUND64()
2120 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K); in LowerFROUND64()
2145 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2153 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT); in LowerFFLOOR()
2154 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE); in LowerFFLOOR()
2155 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc); in LowerFFLOOR()
2157 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero); in LowerFFLOOR()
2159 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add); in LowerFFLOOR()
2167 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerINT_TO_FP64()
2169 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2171 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2174 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2177 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2182 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo); in LowerINT_TO_FP64()
2200 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, in LowerUINT_TO_FP()
2202 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo); in LowerUINT_TO_FP()
2203 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0, in LowerUINT_TO_FP()
2205 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi); in LowerUINT_TO_FP()
2207 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi, in LowerUINT_TO_FP()
2209 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi); in LowerUINT_TO_FP()
2227 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFP64_TO_INT()
2234 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0); in LowerFP64_TO_INT()
2236 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul); in LowerFP64_TO_INT()
2239 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc); in LowerFP64_TO_INT()
2241 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
2243 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma); in LowerFP64_TO_INT()
2245 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi); in LowerFP64_TO_INT()
2247 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result); in LowerFP64_TO_INT()
2289 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp); in LowerSIGN_EXTEND_INREG()
2291 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args); in LowerSIGN_EXTEND_INREG()
2343 if (!ISD::isNormalStore(*I)) in usesAllNormalStores()
2364 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8) in performStoreCombine()
2377 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, in performStoreCombine()
2385 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0)); in performStoreCombine()
2413 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS); in performShlCombine()
2416 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo); in performShlCombine()
2458 case ISD::SHL: { in PerformDAGCombine()
2464 case ISD::MUL: in PerformDAGCombine()
2474 case ISD::SELECT: { in PerformDAGCombine()
2476 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) { in PerformDAGCombine()
2528 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom, in PerformDAGCombine()
2553 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32, in PerformDAGCombine()
2576 case ISD::STORE: in PerformDAGCombine()
2589 const SmallVectorImpl<ISD::InputArg> &Ins, in getOriginalFunctionArgs()
2590 SmallVectorImpl<ISD::InputArg> &OrigIns) const { in getOriginalFunctionArgs()
2612 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used, in getOriginalFunctionArgs()
2806 case ISD::INTRINSIC_WO_CHAIN: { in computeKnownBitsForTargetNode()