35 AMDGPUSubtarget &
36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,  in initializeSubtargetDependencies()
58   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {  in initializeSubtargetDependencies()
65 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,  in AMDGPUSubtarget()  function in AMDGPUSubtarget
69       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),  in AMDGPUSubtarget()
85   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {  in AMDGPUSubtarget()
104 unsigned AMDGPUSubtarget::getStackEntrySize() const {  in getStackEntrySize()
118 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {  in getAmdKernelCodeChipID()
125 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {  in getIsaVersion()
129 bool AMDGPUSubtarget::isVGPRSpillingEnabled(  in isVGPRSpillingEnabled()
134 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,  in overrideSchedPolicy()