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Lines Matching refs:ItinData

2752 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,  in getNumMicroOpsSwiftLdSt()  argument
2757 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3007 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() argument
3009 if (!ItinData || ItinData->isEmpty()) in getNumMicroOps()
3014 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
3017 return getNumMicroOpsSwiftLdSt(ItinData, MI); in getNumMicroOps()
3151 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, in getVLDMDefCycle() argument
3158 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3192 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, in getLDMDefCycle() argument
3199 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3227 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, in getVSTMUseCycle() argument
3233 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3267 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, in getSTMUseCycle() argument
3273 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3296 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
3305 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3314 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
3323 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3344 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); in getOperandLatency()
3355 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
3364 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); in getOperandLatency()
3382 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); in getOperandLatency()
3395 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, in getOperandLatency()
3398 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, in getOperandLatency()
3643 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
3648 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
3690 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
3714 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign, in getOperandLatency()
3733 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, in getOperandLatency() argument
3744 if (!ItinData || ItinData->isEmpty()) in getOperandLatency()
3748 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
3762 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, in getOperandLatency()
3967 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
3982 Latency += getInstrLatency(ItinData, &*I, PredCost); in getInstrLatency()
3995 if (!ItinData) in getInstrLatency()
4001 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency()
4002 return getNumMicroOps(ItinData, MI); in getInstrLatency()
4005 unsigned Latency = ItinData->getStageLatency(Class); in getInstrLatency()
4017 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() argument
4022 if (!ItinData || ItinData->isEmpty()) in getInstrLatency()
4028 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4059 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries(); in hasLowDefLatency() local
4060 if (!ItinData || ItinData->isEmpty()) in hasLowDefLatency()
4066 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()