Lines Matching refs:N0
4444 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts() local
4445 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0); in getCTPOP16BitCounts()
4504 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements() local
4505 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0); in lowerCTPOP32BitElements()
6333 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
6335 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubSExt()
6336 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
6344 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
6346 return N0->hasOneUse() && N1->hasOneUse() && in isAddSubZExt()
6347 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
6358 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
6362 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
6367 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
6374 if (isN1SExt && isAddSubSExt(N0, DAG)) { in LowerMUL()
6377 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { in LowerMUL()
6381 std::swap(N0, N1); in LowerMUL()
6402 Op0 = SkipExtensionForVMULL(N0, DAG); in LowerMUL()
6417 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
6418 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
6420 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
6460 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i16() argument
6467 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6469 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6486 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
6487 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6490 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerSDIV_v4i16()
6491 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
6494 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6495 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerSDIV_v4i16()
6496 return N0; in LowerSDIV_v4i16()
6505 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
6510 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); in LowerSDIV()
6513 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6517 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
6522 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 in LowerSDIV()
6525 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
6526 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerSDIV()
6528 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); in LowerSDIV()
6529 return N0; in LowerSDIV()
6531 return LowerSDIV_v4i16(N0, N1, dl, DAG); in LowerSDIV()
6541 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
6546 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
6549 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6553 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
6558 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 in LowerUDIV()
6561 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
6562 N0 = LowerCONCAT_VECTORS(N0, DAG); in LowerUDIV()
6564 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, in LowerUDIV()
6567 N0); in LowerUDIV()
6568 return N0; in LowerUDIV()
6574 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
6576 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerUDIV()
6598 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerUDIV()
6599 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); in LowerUDIV()
6602 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); in LowerUDIV()
6603 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); in LowerUDIV()
6606 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
6607 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); in LowerUDIV()
6608 return N0; in LowerUDIV()
8361 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
8363 if (N0.getNode()->hasOneUse()) { in combineSelectAndUseCommutative()
8364 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes); in combineSelectAndUseCommutative()
8369 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes); in combineSelectAndUseCommutative()
8378 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADDL() argument
8385 || N0.getOpcode() != ISD::BUILD_VECTOR in AddCombineToVPADDL()
8401 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in AddCombineToVPADDL()
8403 SDValue Vec = N0->getOperand(0)->getOperand(0); in AddCombineToVPADDL()
8410 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { in AddCombineToVPADDL()
8411 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT in AddCombineToVPADDL()
8414 SDValue ExtVec0 = N0->getOperand(i); in AddCombineToVPADDL()
8626 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, in PerformADDCombineWithOperands() argument
8631 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); in PerformADDCombineWithOperands()
8636 if (N0.getNode()->hasOneUse()) { in PerformADDCombineWithOperands()
8637 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); in PerformADDCombineWithOperands()
8648 SDValue N0 = N->getOperand(0); in PerformADDCombine() local
8652 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); in PerformADDCombine()
8657 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); in PerformADDCombine()
8664 SDValue N0 = N->getOperand(0); in PerformSUBCombine() local
8669 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); in PerformSUBCombine()
8698 SDValue N0 = N->getOperand(0); in PerformVMULCombine() local
8700 unsigned Opcode = N0.getOpcode(); in PerformVMULCombine()
8707 std::swap(N0, N1); in PerformVMULCombine()
8710 if (N0 == N1) in PerformVMULCombine()
8715 SDValue N00 = N0->getOperand(0); in PerformVMULCombine()
8716 SDValue N01 = N0->getOperand(1); in PerformVMULCombine()
8892 SDValue N0 = N->getOperand(0); in PerformORCombine() local
8893 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse()) in PerformORCombine()
8905 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); in PerformORCombine()
8921 N0->getOperand(1), in PerformORCombine()
8922 N0->getOperand(0), in PerformORCombine()
8951 SDValue N00 = N0.getOperand(0); in PerformORCombine()
8956 SDValue MaskOp = N0.getOperand(1); in PerformORCombine()
10295 SDValue N0 = N->getOperand(0); in PerformShiftCombine() local
10296 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP && in PerformShiftCombine()
10297 DAG.MaskedValueIsZero(N0.getOperand(0), in PerformShiftCombine()
10299 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1); in PerformShiftCombine()
10339 SDValue N0 = N->getOperand(0); in PerformExtendCombine() local
10345 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
10346 SDValue Vec = N0.getOperand(0); in PerformExtendCombine()
10347 SDValue Lane = N0.getOperand(1); in PerformExtendCombine()
10349 EVT EltVT = N0.getValueType(); in PerformExtendCombine()