Lines Matching refs:FS
177 StringRef CPU, StringRef FS, in ARMBaseTargetMachine() argument
182 CPU, FS, Options, RM, CM, OL), in ARMBaseTargetMachine()
185 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { in ARMBaseTargetMachine()
212 std::string FS = !FSAttr.hasAttribute(Attribute::None) in getSubtargetImpl() local
227 FS += FS.empty() ? "+soft-float" : ",+soft-float"; in getSubtargetImpl()
229 auto &I = SubtargetMap[CPU + FS]; in getSubtargetImpl()
235 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle); in getSubtargetImpl()
249 StringRef CPU, StringRef FS, in ARMTargetMachine() argument
253 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ARMTargetMachine()
263 StringRef CPU, StringRef FS, in ARMLETargetMachine() argument
267 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ARMLETargetMachine()
272 StringRef CPU, StringRef FS, in ARMBETargetMachine() argument
276 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in ARMBETargetMachine()
281 StringRef CPU, StringRef FS, in ThumbTargetMachine() argument
285 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ThumbTargetMachine()
292 StringRef CPU, StringRef FS, in ThumbLETargetMachine() argument
296 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ThumbLETargetMachine()
301 StringRef CPU, StringRef FS, in ThumbBETargetMachine() argument
305 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in ThumbBETargetMachine()