Lines Matching refs:v16i32
197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_Hexagon_VarArg()
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || in CC_HexagonVector()
410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 || in RetCC_Hexagon()
412 LocVT = MVT::v16i32; in RetCC_Hexagon()
413 ValVT = MVT::v16i32; in RetCC_Hexagon()
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
483 if (LocVT == MVT::v16i32) { in RetCC_HexagonVector()
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 || in IsHvxVectorType()
888 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 || in getIndexedAddressParts()
1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 || in LowerFormalArguments()
1568 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass); in HexagonTargetLowering()
2366 MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32; in LowerCONCAT_VECTORS()
2671 case MVT::v16i32: in getRegForInlineAsmConstraint()
2680 case MVT::v16i32: in getRegForInlineAsmConstraint()
2828 case MVT::v16i32: in findRepresentativeClass()