Lines Matching refs:RO
179 RegisterOperand RO> :
180 InstSE<(outs), (ins RO:$rs, opnd:$offset),
189 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
191 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
193 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
199 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
201 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
203 [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> {
222 class MovePMM16<string opstr, RegisterOperand RO> :
223 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
266 class LLEBaseMM<string opstr, RegisterOperand RO> :
267 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
273 class SCBaseMM<string opstr, RegisterOperand RO> :
274 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
281 class SCEBaseMM<string opstr, RegisterOperand RO> :
282 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
289 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
291 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
293 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
299 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
302 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
304 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
308 class AndImmMM16<string opstr, RegisterOperand RO,
310 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
313 class LogicRMM16<string opstr, RegisterOperand RO,
316 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
318 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
323 class NotMM16<string opstr, RegisterOperand RO> :
324 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
326 [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
328 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
330 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
333 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
335 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
342 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
351 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
353 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
360 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
362 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
368 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
370 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
377 class AddImmUR2<string opstr, RegisterOperand RO> :
378 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
384 class AddImmUS5<string opstr, RegisterOperand RO> :
385 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
390 class AddImmUR1SP<string opstr, RegisterOperand RO> :
391 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
398 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
399 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
405 class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
407 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
413 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
414 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
420 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
421 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
422 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
429 class JumpRegMM16<string opstr, RegisterOperand RO> :
430 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
448 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
449 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
457 class JumpRegCMM16<string opstr, RegisterOperand RO> :
458 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
472 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
473 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
489 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
490 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
494 RegisterOperand RO> :
495 InstSE<(outs), (ins RO:$rs, opnd:$offset),
499 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
502 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
509 class AddImmUPC<string opstr, RegisterOperand RO> :
510 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),