Lines Matching refs:RO
784 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
787 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
789 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
796 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
800 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
802 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
818 class LogicNOR<string opstr, RegisterOperand RO>:
819 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
821 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
827 RegisterOperand RO, InstrItinClass itin,
830 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
832 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
836 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
838 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
840 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
844 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
845 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
852 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
854 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
855 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
861 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
864 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
865 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
870 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
872 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
876 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
878 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
880 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
885 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
887 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
888 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
928 RegisterOperand RO, bit DelaySlot = 1> :
929 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
931 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
940 RegisterOperand RO, bit DelaySlot = 1> :
941 InstSE<(outs), (ins RO:$rs, opnd:$offset),
943 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
952 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
953 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
955 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
959 RegisterOperand RO>:
960 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
962 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
991 class JumpFR<string opstr, RegisterOperand RO,
993 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
997 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
1010 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
1011 Register RetReg, RegisterOperand ResRO = RO>:
1012 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
1015 class JumpLinkReg<string opstr, RegisterOperand RO>:
1016 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1020 RegisterOperand RO, bit DelaySlot = 1> :
1021 InstSE<(outs), (ins RO:$rs, opnd:$offset),
1034 class TailCallReg<RegisterOperand RO, Instruction JRInst,
1035 RegisterOperand ResRO = RO> :
1036 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1066 class DEI_FT<string opstr, RegisterOperand RO> :
1067 InstSE<(outs RO:$rt), (ins),
1088 class TEQ_FT<string opstr, RegisterOperand RO> :
1089 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
1093 class TEQI_FT<string opstr, RegisterOperand RO> :
1094 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
1097 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1099 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1133 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1135 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1145 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1146 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1157 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1158 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1164 class EffectiveAddress<string opstr, RegisterOperand RO> :
1165 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1166 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1173 class CountLeading0<string opstr, RegisterOperand RO>:
1174 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1175 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1177 class CountLeading1<string opstr, RegisterOperand RO>:
1178 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1179 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1182 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1184 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1185 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1188 class SubwordSwap<string opstr, RegisterOperand RO,
1190 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1196 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1197 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1201 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1203 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
1205 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1208 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1210 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1212 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1227 class LLBase<string opstr, RegisterOperand RO> :
1228 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1234 class SCBase<string opstr, RegisterOperand RO> :
1235 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1242 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1243 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1246 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1247 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1557 class PseudoIndirectBranchBase<RegisterOperand RO> :
1558 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1573 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1929 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1930 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1935 RegisterOperand RO> :
1936 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1940 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1941 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),