Lines Matching refs:I2
167 bits<16> I2;
172 let Inst{15-0} = I2;
200 bits<8> I2;
208 let Inst{15-8} = I2;
219 bits<16> I2;
224 let Inst{31-16} = I2;
255 bits<32> I2;
260 let Inst{31-0} = I2;
432 bits<8> I2;
435 let Inst{23-16} = I2;
445 bits<16> I2;
449 let Inst{15-0} = I2;
458 bits<8> I2;
461 let Inst{39-32} = I2;
498 bits<16> I2;
504 let Inst{31-16} = I2;
517 bits<8> I2;
524 let Inst{31-24} = I2;
539 bits<16> I2;
545 let Inst{31-16} = I2;
964 let I2 = value;
969 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$I2),
970 mnemonic##"\t$R1, $I2", []> {
992 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
993 mnemonic#"\t$R1, $I2",
994 [(operator cls:$R1, pcrel32:$I2)]> {
1079 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1080 mnemonic#"\t$BD1, $I2",
1081 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1087 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
1088 mnemonic#"\t$BD1, $I2",
1089 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
1095 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
1096 mnemonic#"\t$BD1, $I2",
1097 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
1215 : InstRI<opcode, (outs cls:$R1), (ins imm:$I2),
1216 mnemonic#"\t$R1, $I2",
1217 [(set cls:$R1, (operator imm:$I2))]>;
1221 : InstRIL<opcode, (outs cls:$R1), (ins imm:$I2),
1222 mnemonic#"\t$R1, $I2",
1223 [(set cls:$R1, (operator imm:$I2))]>;
1227 : InstRIL<opcode, (outs cls:$R1), (ins pcrel32:$I2),
1228 mnemonic#"\t$R1, $I2",
1229 [(set cls:$R1, (operator pcrel32:$I2))]> {
1332 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
1333 mnemonic#"\t$V1, $I2",
1334 [(set tr.op:$V1, (tr.vt (operator imm:$I2)))]> {
1436 : InstRI<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1437 mnemonic#"\t$R1, $I2",
1438 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1445 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
1446 mnemonic#"\t$R1, $R3, $I2",
1447 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
1463 : InstRIL<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
1464 mnemonic#"\t$R1, $I2",
1465 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
1555 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1556 mnemonic#"\t$BD1, $I2",
1557 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1564 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1565 mnemonic#"\t$BD1, $I2",
1566 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
1584 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
1585 mnemonic#"\t$V1, $I2, $I3",
1586 [(set tr.op:$V1, (tr.vt (operator imm32zx8:$I2, imm32zx8:$I3)))]> {
1592 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
1593 mnemonic#"\t$V1, $V3, $I2",
1595 imm32zx16:$I2)))]> {
1746 : InstRI<opcode, (outs), (ins cls:$R1, imm:$I2),
1747 mnemonic#"\t$R1, $I2",
1748 [(operator cls:$R1, imm:$I2)]> {
1754 : InstRIL<opcode, (outs), (ins cls:$R1, imm:$I2),
1755 mnemonic#"\t$R1, $I2",
1756 [(operator cls:$R1, imm:$I2)]> {
1762 : InstRIL<opcode, (outs), (ins cls:$R1, pcrel32:$I2),
1763 mnemonic#"\t$R1, $I2",
1764 [(operator cls:$R1, (load pcrel32:$I2))]> {
1828 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
1829 mnemonic#"\t$BD1, $I2",
1830 [(operator (load mode:$BD1), imm:$I2)]> {
1837 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
1838 mnemonic#"\t$BD1, $I2",
1839 [(operator (load bdaddr12only:$BD1), imm:$I2)]> {
1847 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
1848 mnemonic#"\t$BD1, $I2",
1849 [(operator (load mode:$BD1), imm:$I2)]> {
1905 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
1906 mnemonic#"\t$V1, $I2, $M3",
1908 imm:$I2, index:$M3)))]> {
2143 : InstRIL<opcode, (outs), (ins imm32zx4:$R1, pcrel32:$I2),
2144 mnemonic##"\t$R1, $I2",
2145 [(operator imm32zx4:$R1, pcrel32:$I2)]> {
2183 : Pseudo<(outs cls:$R1), (ins imm:$I2),
2184 [(set cls:$R1, (operator imm:$I2))]>;
2212 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
2213 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2220 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
2221 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
2239 : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>;
2428 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2429 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2436 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
2437 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
2448 : Alias<4, (outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]> {