Lines Matching refs:R2
9 …enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN
12 …enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN
15 …mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN
18 …mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN
31 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
33 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
34 ; 32R2: add.s $f0, $[[T1]], $[[T2]]
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
47 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
48 ; 64R2: add.s $f0, $[[T0]], $[[T1]]
71 ; 32R2: mtc1 $6, $[[T0:f[0-9]+]]
72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
73 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
74 ; 32R2: add.s $f0, $[[T1]], $[[T2]]
86 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
87 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
88 ; 64R2: add.s $f0, $[[T0]], $[[T1]]
111 ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
112 ; 32R2-NONAN: nmadd.s $f0, $[[T0]], $f12, $f14
114 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
115 ; 32R2-NAN: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
116 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
117 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
131 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
134 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
135 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
158 ; 32R2-NONAN: mtc1 $6, $[[T0:f[0-9]+]]
159 ; 32R2-NONAN: nmsub.s $f0, $[[T0]], $f12, $f14
161 ; 32R2-NAN: mtc1 $6, $[[T0:f[0-9]+]]
162 ; 32R2-NAN: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
163 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
164 ; 32R2-NAN: sub.s $f0, $[[T2]], $[[T1]]
172 ; 64R2-NAN: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
173 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
174 ; 64R2-NAN: sub.s $f0, $[[T1]], $[[T0]]
197 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
198 ; 32R2: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
199 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
200 ; 32R2: mthc1 $zero, $[[T2]]
201 ; 32R2: add.d $f0, $[[T1]], $[[T2]]
213 ; 64R2: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
214 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
215 ; 64R2: add.d $f0, $[[T0]], $[[T1]]
238 ; 32R2: ldc1 $[[T0:f[0-9]+]], 16($sp)
239 ; 32R2: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
240 ; 32R2: mtc1 $zero, $[[T2:f[0-9]+]]
241 ; 32R2: mthc1 $zero, $[[T2]]
242 ; 32R2: add.d $f0, $[[T1]], $[[T2]]
254 ; 64R2: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
255 ; 64R2: mtc1 $zero, $[[T1:f[0-9]+]]
256 ; 64R2: add.d $f0, $[[T0]], $[[T1]]
279 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
280 ; 32R2-NONAN: nmadd.d $f0, $[[T0]], $f12, $f14
282 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
283 ; 32R2-NAN: madd.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
284 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
285 ; 32R2-NAN: mthc1 $zero, $[[T2]]
286 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
300 ; 64R2-NONAN: nmadd.d $f0, $f14, $f12, $f13
302 ; 64R2-NAN: madd.d $[[T0:f[0-9]+]], $f14, $f12, $f13
303 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
304 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]
327 ; 32R2-NONAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
328 ; 32R2-NONAN: nmsub.d $f0, $[[T0]], $f12, $f14
330 ; 32R2-NAN: ldc1 $[[T0:f[0-9]+]], 16($sp)
331 ; 32R2-NAN: msub.d $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
332 ; 32R2-NAN: mtc1 $zero, $[[T2:f[0-9]+]]
333 ; 32R2-NAN: mthc1 $zero, $[[T2]]
334 ; 32R2-NAN: sub.d $f0, $[[T2]], $[[T1]]
348 ; 64R2-NONAN: nmsub.d $f0, $f14, $f12, $f13
350 ; 64R2-NAN: msub.d $[[T0:f[0-9]+]], $f14, $f12, $f13
351 ; 64R2-NAN: mtc1 $zero, $[[T1:f[0-9]+]]
352 ; 64R2-NAN: sub.d $f0, $[[T1]], $[[T0]]