Lines Matching refs:DAG
53 DebugLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
70 DebugLoc DL, SelectionDAG &DAG) const in LowerReturn()
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) in LowerOperation()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
93 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
102 SelectionDAG &DAG) const in LowerINTRINSIC_WO_CHAIN()
111 return LowerIntrinsicIABS(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
117 return LowerIntrinsicLRP(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
139 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
142 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
144 return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
150 SelectionDAG &DAG) const in LowerIntrinsicIABS()
155 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), in LowerIntrinsicIABS()
158 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); in LowerIntrinsicIABS()
164 SelectionDAG &DAG) const in LowerIntrinsicLRP()
168 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, in LowerIntrinsicLRP()
169 DAG.getConstantFP(1.0f, MVT::f32), in LowerIntrinsicLRP()
171 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, in LowerIntrinsicLRP()
173 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerIntrinsicLRP()
181 SelectionDAG &DAG) const in LowerUDIVREM()
193 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den); in LowerUDIVREM()
196 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den); in LowerUDIVREM()
199 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
202 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), in LowerUDIVREM()
206 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT), in LowerUDIVREM()
211 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
214 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E); in LowerUDIVREM()
217 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); in LowerUDIVREM()
220 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT), in LowerUDIVREM()
224 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
227 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den); in LowerUDIVREM()
230 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder); in LowerUDIVREM()
233 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den, in LowerUDIVREM()
234 DAG.getConstant(-1, VT), in LowerUDIVREM()
235 DAG.getConstant(0, VT), in LowerUDIVREM()
238 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder, in LowerUDIVREM()
239 DAG.getConstant(0, VT), in LowerUDIVREM()
240 DAG.getConstant(-1, VT), in LowerUDIVREM()
241 DAG.getConstant(0, VT), in LowerUDIVREM()
244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, in LowerUDIVREM()
250 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient, in LowerUDIVREM()
251 DAG.getConstant(1, VT)); in LowerUDIVREM()
254 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, in LowerUDIVREM()
255 DAG.getConstant(1, VT)); in LowerUDIVREM()
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
262 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT), in LowerUDIVREM()
268 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den); in LowerUDIVREM()
271 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den); in LowerUDIVREM()
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT), in LowerUDIVREM()
278 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT), in LowerUDIVREM()
281 DAG.ReplaceAllUsesWith(Op.getValue(0).getNode(), &Div); in LowerUDIVREM()
282 DAG.ReplaceAllUsesWith(Op.getValue(1).getNode(), &Rem); in LowerUDIVREM()
313 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG, in CreateLiveInRegister() argument
316 MachineFunction &MF = DAG.getMachineFunction(); in CreateLiveInRegister()
325 return DAG.getRegister(VirtualRegister, VT); in CreateLiveInRegister()