Lines Matching refs:pm4
42 struct si_pm4_state *pm4; in si_update_fb_blend_state() local
49 pm4 = CALLOC_STRUCT(si_pm4_state); in si_update_fb_blend_state()
50 if (pm4 == NULL) in si_update_fb_blend_state()
55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); in si_update_fb_blend_state()
57 si_pm4_set_state(rctx, fb_blend, pm4); in si_update_fb_blend_state()
138 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state() local
151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state()
153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); in si_create_blend_state()
154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); in si_create_blend_state()
174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state()
189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state()
212 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_blend_color() local
214 if (pm4 == NULL) in si_set_blend_color()
217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); in si_set_blend_color()
218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); in si_set_blend_color()
219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); in si_set_blend_color()
220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); in si_set_blend_color()
222 si_pm4_set_state(rctx, blend_color, pm4); in si_set_blend_color()
233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_clip_state() local
235 if (pm4 == NULL) in si_set_clip_state()
239 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, in si_set_clip_state()
241 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, in si_set_clip_state()
243 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, in si_set_clip_state()
245 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, in si_set_clip_state()
249 si_pm4_set_state(rctx, clip, pm4); in si_set_clip_state()
256 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_scissor_state() local
259 if (pm4 == NULL) in si_set_scissor_state()
264 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); in si_set_scissor_state()
265 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); in si_set_scissor_state()
266 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); in si_set_scissor_state()
267 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); in si_set_scissor_state()
268 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); in si_set_scissor_state()
269 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); in si_set_scissor_state()
270 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); in si_set_scissor_state()
271 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); in si_set_scissor_state()
273 si_pm4_set_state(rctx, scissor, pm4); in si_set_scissor_state()
281 struct si_pm4_state *pm4 = &viewport->pm4; in si_set_viewport_state() local
287 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); in si_set_viewport_state()
288 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); in si_set_viewport_state()
289 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); in si_set_viewport_state()
290 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); in si_set_viewport_state()
291 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); in si_set_viewport_state()
292 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); in si_set_viewport_state()
293 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); in si_set_viewport_state()
294 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); in si_set_viewport_state()
295 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); in si_set_viewport_state()
306 struct si_pm4_state *pm4; in si_update_fb_rs_state() local
334 pm4 = CALLOC_STRUCT(si_pm4_state); in si_update_fb_rs_state()
337 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, in si_update_fb_rs_state()
339 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); in si_update_fb_rs_state()
340 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, in si_update_fb_rs_state()
342 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); in si_update_fb_rs_state()
343 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); in si_update_fb_rs_state()
345 si_pm4_set_state(rctx, fb_rs, pm4); in si_update_fb_rs_state()
371 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
430 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); in si_create_rs_state()
432 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); in si_create_rs_state()
435 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); in si_create_rs_state()
446 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, in si_create_rs_state()
451 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); in si_create_rs_state()
452 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, in si_create_rs_state()
455 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); in si_create_rs_state()
456 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, in si_create_rs_state()
458 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); in si_create_rs_state()
459 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); in si_create_rs_state()
460 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); in si_create_rs_state()
461 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); in si_create_rs_state()
463 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); in si_create_rs_state()
464 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); in si_create_rs_state()
499 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_update_dsa_stencil_ref() local
503 if (pm4 == NULL) in si_update_dsa_stencil_ref()
506 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, in si_update_dsa_stencil_ref()
510 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, in si_update_dsa_stencil_ref()
515 si_pm4_set_state(rctx, dsa_stencil_ref, pm4); in si_update_dsa_stencil_ref()
562 struct si_pm4_state *pm4 = &dsa->pm4; in si_create_dsa_state() local
613 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); in si_create_dsa_state()
614 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); in si_create_dsa_state()
615 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); in si_create_dsa_state()
616 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); in si_create_dsa_state()
618 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); in si_create_dsa_state()
619 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); in si_create_dsa_state()
620 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override); in si_create_dsa_state()
621 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); in si_create_dsa_state()
622 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); in si_create_dsa_state()
623 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); in si_create_dsa_state()
624 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); in si_create_dsa_state()
625 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); in si_create_dsa_state()
661 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, in si_create_db_flush_dsa()
1444 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, in si_cb() argument
1585 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); in si_cb()
1586 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); in si_cb()
1587 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); in si_cb()
1588 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); in si_cb()
1591 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000); in si_cb()
1593 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, in si_cb()
1597 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); in si_cb()
1598 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); in si_cb()
1612 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, in si_db() argument
1622 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); in si_db()
1623 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); in si_db()
1675 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); in si_db()
1676 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); in si_db()
1680 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, in si_db()
1684 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1); in si_db()
1686 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); in si_db()
1689 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); in si_db()
1693 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); in si_db()
1695 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); in si_db()
1698 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); in si_db()
1699 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); in si_db()
1700 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); in si_db()
1701 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); in si_db()
1702 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); in si_db()
1704 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); in si_db()
1705 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); in si_db()
1712 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_framebuffer_state() local
1716 if (pm4 == NULL) in si_set_framebuffer_state()
1719 si_pm4_inval_fb_cache(pm4, state->nr_cbufs); in si_set_framebuffer_state()
1722 si_pm4_inval_zsbuf_cache(pm4); in si_set_framebuffer_state()
1731 si_cb(rctx, pm4, state, i); in si_set_framebuffer_state()
1734 si_db(rctx, pm4, state); in si_set_framebuffer_state()
1759 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); in si_set_framebuffer_state()
1760 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); in si_set_framebuffer_state()
1761 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); in si_set_framebuffer_state()
1762 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); in si_set_framebuffer_state()
1763 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); in si_set_framebuffer_state()
1764 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); in si_set_framebuffer_state()
1765 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); in si_set_framebuffer_state()
1766 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); in si_set_framebuffer_state()
1767 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); in si_set_framebuffer_state()
1768 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); in si_set_framebuffer_state()
1769 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask); in si_set_framebuffer_state()
1770 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, in si_set_framebuffer_state()
1772 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); in si_set_framebuffer_state()
1774 si_pm4_set_state(rctx, framebuffer, pm4); in si_set_framebuffer_state()
1916 si_pm4_bind_state(rctx, vs, sel->current->pm4); in si_bind_vs_shader()
1918 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); in si_bind_vs_shader()
1933 si_pm4_bind_state(rctx, ps, sel->current->pm4); in si_bind_ps_shader()
1935 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4); in si_bind_ps_shader()
1946 si_pm4_delete_state(rctx, vs, p->pm4); in si_delete_shader_selector()
2176 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0])); in si_create_sampler_state()
2177 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1])); in si_create_sampler_state()
2178 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2])); in si_create_sampler_state()
2179 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3])); in si_create_sampler_state()
2196 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_ps_sampler_view() local
2203 si_pm4_inval_texture_cache(pm4); in si_set_ps_sampler_view()
2205 si_pm4_sh_data_begin(pm4); in si_set_ps_sampler_view()
2214 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ); in si_set_ps_sampler_view()
2217 si_pm4_sh_data_add(pm4, resource[i]->state[j]); in si_set_ps_sampler_view()
2227 si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4); in si_set_ps_sampler_view()
2230 si_pm4_set_state(rctx, ps_sampler_views, pm4); in si_set_ps_sampler_view()
2244 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_bind_ps_sampler() local
2250 si_pm4_inval_texture_cache(pm4); in si_bind_ps_sampler()
2252 si_pm4_sh_data_begin(pm4); in si_bind_ps_sampler()
2255 si_pm4_sh_data_add(pm4, rstates[i]->val[j]); in si_bind_ps_sampler()
2258 si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2); in si_bind_ps_sampler()
2263 si_pm4_set_state(rctx, ps_sampler, pm4); in si_bind_ps_sampler()
2284 struct si_pm4_state *pm4; in si_set_constant_buffer() local
2294 pm4 = CALLOC_STRUCT(si_pm4_state); in si_set_constant_buffer()
2295 si_pm4_inval_shader_cache(pm4); in si_set_constant_buffer()
2304 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); in si_set_constant_buffer()
2308 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset); in si_set_constant_buffer()
2309 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32); in si_set_constant_buffer()
2310 si_pm4_set_state(rctx, vs_const, pm4); in si_set_constant_buffer()
2314 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset); in si_set_constant_buffer()
2315 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32); in si_set_constant_buffer()
2316 si_pm4_set_state(rctx, ps_const, pm4); in si_set_constant_buffer()
2429 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_texture_barrier() local
2431 si_pm4_inval_texture_cache(pm4); in si_texture_barrier()
2432 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); in si_texture_barrier()
2433 si_pm4_set_state(rctx, texture_barrier, pm4); in si_texture_barrier()
2498 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_init_config() local
2500 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); in si_init_config()
2501 si_pm4_cmd_add(pm4, 0x80000000); in si_init_config()
2502 si_pm4_cmd_add(pm4, 0x80000000); in si_init_config()
2503 si_pm4_cmd_end(pm4, false); in si_init_config()
2505 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); in si_init_config()
2507 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); in si_init_config()
2508 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); in si_init_config()
2509 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); in si_init_config()
2510 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); in si_init_config()
2511 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); in si_init_config()
2512 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); in si_init_config()
2513 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); in si_init_config()
2514 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); in si_init_config()
2515 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); in si_init_config()
2516 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); in si_init_config()
2517 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); in si_init_config()
2518 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); in si_init_config()
2519 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); in si_init_config()
2520 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); in si_init_config()
2521 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_init_config()
2522 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); in si_init_config()
2523 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); in si_init_config()
2524 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, in si_init_config()
2528 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); in si_init_config()
2529 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); in si_init_config()
2530 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); in si_init_config()
2532 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); in si_init_config()
2533 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); in si_init_config()
2534 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); in si_init_config()
2536 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); in si_init_config()
2538 si_pm4_set_state(rctx, init, pm4); in si_init_config()