Lines Matching refs:rd
1080 void Assembler::adr(const Register& rd, int imm21) { in adr() argument
1081 DCHECK(rd.Is64Bits()); in adr()
1082 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
1086 void Assembler::adr(const Register& rd, Label* label) { in adr() argument
1087 adr(rd, LinkAndGetByteOffsetTo(label)); in adr()
1091 void Assembler::add(const Register& rd, in add() argument
1094 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1098 void Assembler::adds(const Register& rd, in adds() argument
1101 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1112 void Assembler::sub(const Register& rd, in sub() argument
1115 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
1119 void Assembler::subs(const Register& rd, in subs() argument
1122 AddSub(rd, rn, operand, SetFlags, SUB); in subs()
1132 void Assembler::neg(const Register& rd, const Operand& operand) { in neg() argument
1133 Register zr = AppropriateZeroRegFor(rd); in neg()
1134 sub(rd, zr, operand); in neg()
1138 void Assembler::negs(const Register& rd, const Operand& operand) { in negs() argument
1139 Register zr = AppropriateZeroRegFor(rd); in negs()
1140 subs(rd, zr, operand); in negs()
1144 void Assembler::adc(const Register& rd, in adc() argument
1147 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC); in adc()
1151 void Assembler::adcs(const Register& rd, in adcs() argument
1154 AddSubWithCarry(rd, rn, operand, SetFlags, ADC); in adcs()
1158 void Assembler::sbc(const Register& rd, in sbc() argument
1161 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC); in sbc()
1165 void Assembler::sbcs(const Register& rd, in sbcs() argument
1168 AddSubWithCarry(rd, rn, operand, SetFlags, SBC); in sbcs()
1172 void Assembler::ngc(const Register& rd, const Operand& operand) { in ngc() argument
1173 Register zr = AppropriateZeroRegFor(rd); in ngc()
1174 sbc(rd, zr, operand); in ngc()
1178 void Assembler::ngcs(const Register& rd, const Operand& operand) { in ngcs() argument
1179 Register zr = AppropriateZeroRegFor(rd); in ngcs()
1180 sbcs(rd, zr, operand); in ngcs()
1185 void Assembler::and_(const Register& rd, in and_() argument
1188 Logical(rd, rn, operand, AND); in and_()
1192 void Assembler::ands(const Register& rd, in ands() argument
1195 Logical(rd, rn, operand, ANDS); in ands()
1205 void Assembler::bic(const Register& rd, in bic() argument
1208 Logical(rd, rn, operand, BIC); in bic()
1212 void Assembler::bics(const Register& rd, in bics() argument
1215 Logical(rd, rn, operand, BICS); in bics()
1219 void Assembler::orr(const Register& rd, in orr() argument
1222 Logical(rd, rn, operand, ORR); in orr()
1226 void Assembler::orn(const Register& rd, in orn() argument
1229 Logical(rd, rn, operand, ORN); in orn()
1233 void Assembler::eor(const Register& rd, in eor() argument
1236 Logical(rd, rn, operand, EOR); in eor()
1240 void Assembler::eon(const Register& rd, in eon() argument
1243 Logical(rd, rn, operand, EON); in eon()
1247 void Assembler::lslv(const Register& rd, in lslv() argument
1250 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lslv()
1251 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in lslv()
1252 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1256 void Assembler::lsrv(const Register& rd, in lsrv() argument
1259 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lsrv()
1260 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in lsrv()
1261 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1265 void Assembler::asrv(const Register& rd, in asrv() argument
1268 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in asrv()
1269 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in asrv()
1270 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1274 void Assembler::rorv(const Register& rd, in rorv() argument
1277 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in rorv()
1278 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in rorv()
1279 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1284 void Assembler::bfm(const Register& rd, const Register& rn, int immr, in bfm() argument
1286 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in bfm()
1287 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in bfm()
1288 Emit(SF(rd) | BFM | N | in bfm()
1289 ImmR(immr, rd.SizeInBits()) | in bfm()
1291 Rn(rn) | Rd(rd)); in bfm()
1295 void Assembler::sbfm(const Register& rd, const Register& rn, int immr, in sbfm() argument
1297 DCHECK(rd.Is64Bits() || rn.Is32Bits()); in sbfm()
1298 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in sbfm()
1299 Emit(SF(rd) | SBFM | N | in sbfm()
1300 ImmR(immr, rd.SizeInBits()) | in sbfm()
1302 Rn(rn) | Rd(rd)); in sbfm()
1306 void Assembler::ubfm(const Register& rd, const Register& rn, int immr, in ubfm() argument
1308 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ubfm()
1309 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in ubfm()
1310 Emit(SF(rd) | UBFM | N | in ubfm()
1311 ImmR(immr, rd.SizeInBits()) | in ubfm()
1313 Rn(rn) | Rd(rd)); in ubfm()
1317 void Assembler::extr(const Register& rd, const Register& rn, const Register& rm, in extr() argument
1319 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in extr()
1320 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in extr()
1321 Instr N = SF(rd) >> (kSFOffset - kBitfieldNOffset); in extr()
1322 Emit(SF(rd) | EXTR | N | Rm(rm) | in extr()
1323 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in extr()
1327 void Assembler::csel(const Register& rd, in csel() argument
1331 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
1335 void Assembler::csinc(const Register& rd, in csinc() argument
1339 ConditionalSelect(rd, rn, rm, cond, CSINC); in csinc()
1343 void Assembler::csinv(const Register& rd, in csinv() argument
1347 ConditionalSelect(rd, rn, rm, cond, CSINV); in csinv()
1351 void Assembler::csneg(const Register& rd, in csneg() argument
1355 ConditionalSelect(rd, rn, rm, cond, CSNEG); in csneg()
1359 void Assembler::cset(const Register &rd, Condition cond) { in cset() argument
1361 Register zr = AppropriateZeroRegFor(rd); in cset()
1362 csinc(rd, zr, zr, NegateCondition(cond)); in cset()
1366 void Assembler::csetm(const Register &rd, Condition cond) { in csetm() argument
1368 Register zr = AppropriateZeroRegFor(rd); in csetm()
1369 csinv(rd, zr, zr, NegateCondition(cond)); in csetm()
1373 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) { in cinc() argument
1375 csinc(rd, rn, rn, NegateCondition(cond)); in cinc()
1379 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) { in cinv() argument
1381 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
1385 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) { in cneg() argument
1387 csneg(rd, rn, rn, NegateCondition(cond)); in cneg()
1391 void Assembler::ConditionalSelect(const Register& rd, in ConditionalSelect() argument
1396 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ConditionalSelect()
1397 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in ConditionalSelect()
1398 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
1418 void Assembler::DataProcessing3Source(const Register& rd, in DataProcessing3Source() argument
1423 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
1427 void Assembler::mul(const Register& rd, in mul() argument
1430 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mul()
1432 DataProcessing3Source(rd, rn, rm, zr, MADD); in mul()
1436 void Assembler::madd(const Register& rd, in madd() argument
1440 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in madd()
1441 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
1445 void Assembler::mneg(const Register& rd, in mneg() argument
1448 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mneg()
1450 DataProcessing3Source(rd, rn, rm, zr, MSUB); in mneg()
1454 void Assembler::msub(const Register& rd, in msub() argument
1458 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in msub()
1459 DataProcessing3Source(rd, rn, rm, ra, MSUB); in msub()
1463 void Assembler::smaddl(const Register& rd, in smaddl() argument
1467 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in smaddl()
1469 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x); in smaddl()
1473 void Assembler::smsubl(const Register& rd, in smsubl() argument
1477 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in smsubl()
1479 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x); in smsubl()
1483 void Assembler::umaddl(const Register& rd, in umaddl() argument
1487 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in umaddl()
1489 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x); in umaddl()
1493 void Assembler::umsubl(const Register& rd, in umsubl() argument
1497 DCHECK(rd.Is64Bits() && ra.Is64Bits()); in umsubl()
1499 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x); in umsubl()
1503 void Assembler::smull(const Register& rd, in smull() argument
1506 DCHECK(rd.Is64Bits()); in smull()
1508 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x); in smull()
1512 void Assembler::smulh(const Register& rd, in smulh() argument
1515 DCHECK(AreSameSizeAndType(rd, rn, rm)); in smulh()
1516 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x); in smulh()
1520 void Assembler::sdiv(const Register& rd, in sdiv() argument
1523 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in sdiv()
1524 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in sdiv()
1525 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
1529 void Assembler::udiv(const Register& rd, in udiv() argument
1532 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in udiv()
1533 DCHECK(rd.SizeInBits() == rm.SizeInBits()); in udiv()
1534 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1538 void Assembler::rbit(const Register& rd, in rbit() argument
1540 DataProcessing1Source(rd, rn, RBIT); in rbit()
1544 void Assembler::rev16(const Register& rd, in rev16() argument
1546 DataProcessing1Source(rd, rn, REV16); in rev16()
1550 void Assembler::rev32(const Register& rd, in rev32() argument
1552 DCHECK(rd.Is64Bits()); in rev32()
1553 DataProcessing1Source(rd, rn, REV); in rev32()
1557 void Assembler::rev(const Register& rd, in rev() argument
1559 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w); in rev()
1563 void Assembler::clz(const Register& rd, in clz() argument
1565 DataProcessing1Source(rd, rn, CLZ); in clz()
1569 void Assembler::cls(const Register& rd, in cls() argument
1571 DataProcessing1Source(rd, rn, CLS); in cls()
1696 void Assembler::mov(const Register& rd, const Register& rm) { in mov() argument
1700 if (rd.IsSP() || rm.IsSP()) { in mov()
1701 add(rd, rm, 0); in mov()
1703 orr(rd, AppropriateZeroRegFor(rd), rm); in mov()
1708 void Assembler::mvn(const Register& rd, const Operand& operand) { in mvn() argument
1709 orn(rd, AppropriateZeroRegFor(rd), operand); in mvn()
1759 void Assembler::fmov(Register rd, FPRegister fn) { in fmov() argument
1760 DCHECK(rd.SizeInBits() == fn.SizeInBits()); in fmov()
1761 FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd; in fmov()
1762 Emit(op | Rd(rd) | Rn(fn)); in fmov()
1959 void Assembler::FPConvertToInt(const Register& rd, in FPConvertToInt() argument
1962 Emit(SF(rd) | FPType(fn) | op | Rn(fn) | Rd(rd)); in FPConvertToInt()
1980 void Assembler::fcvtau(const Register& rd, const FPRegister& fn) { in fcvtau() argument
1981 FPConvertToInt(rd, fn, FCVTAU); in fcvtau()
1985 void Assembler::fcvtas(const Register& rd, const FPRegister& fn) { in fcvtas() argument
1986 FPConvertToInt(rd, fn, FCVTAS); in fcvtas()
1990 void Assembler::fcvtmu(const Register& rd, const FPRegister& fn) { in fcvtmu() argument
1991 FPConvertToInt(rd, fn, FCVTMU); in fcvtmu()
1995 void Assembler::fcvtms(const Register& rd, const FPRegister& fn) { in fcvtms() argument
1996 FPConvertToInt(rd, fn, FCVTMS); in fcvtms()
2000 void Assembler::fcvtnu(const Register& rd, const FPRegister& fn) { in fcvtnu() argument
2001 FPConvertToInt(rd, fn, FCVTNU); in fcvtnu()
2005 void Assembler::fcvtns(const Register& rd, const FPRegister& fn) { in fcvtns() argument
2006 FPConvertToInt(rd, fn, FCVTNS); in fcvtns()
2010 void Assembler::fcvtzu(const Register& rd, const FPRegister& fn) { in fcvtzu() argument
2011 FPConvertToInt(rd, fn, FCVTZU); in fcvtzu()
2015 void Assembler::fcvtzs(const Register& rd, const FPRegister& fn) { in fcvtzs() argument
2016 FPConvertToInt(rd, fn, FCVTZS); in fcvtzs()
2124 void Assembler::MoveWide(const Register& rd, in MoveWide() argument
2129 if (rd.Is32Bits()) { in MoveWide()
2140 DCHECK(rd.Is64Bits() || (shift == 0) || (shift == 16)); in MoveWide()
2152 DCHECK(rd.Is64Bits()); in MoveWide()
2156 DCHECK(rd.Is64Bits()); in MoveWide()
2164 Emit(SF(rd) | MoveWideImmediateFixed | mov_op | Rd(rd) | in MoveWide()
2169 void Assembler::AddSub(const Register& rd, in AddSub() argument
2174 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSub()
2179 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd); in AddSub()
2180 Emit(SF(rd) | AddSubImmediateFixed | op | Flags(S) | in AddSub()
2183 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits()); in AddSub()
2193 if (rn.IsSP() || rd.IsSP()) { in AddSub()
2194 DCHECK(!(rd.IsSP() && (S == SetFlags))); in AddSub()
2195 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S, in AddSub()
2198 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op); in AddSub()
2202 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op); in AddSub()
2207 void Assembler::AddSubWithCarry(const Register& rd, in AddSubWithCarry() argument
2212 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSubWithCarry()
2213 DCHECK(rd.SizeInBits() == operand.reg().SizeInBits()); in AddSubWithCarry()
2216 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd)); in AddSubWithCarry()
2277 void Assembler::Logical(const Register& rd, in Logical() argument
2281 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in Logical()
2285 unsigned reg_size = rd.SizeInBits(); in Logical()
2289 DCHECK(rd.Is64Bits() || is_uint32(immediate)); in Logical()
2294 immediate = rd.Is64Bits() ? ~immediate : (~immediate & kWRegMask); in Logical()
2300 LogicalImmediate(rd, rn, n, imm_s, imm_r, op); in Logical()
2307 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits()); in Logical()
2309 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op); in Logical()
2314 void Assembler::LogicalImmediate(const Register& rd, in LogicalImmediate() argument
2320 unsigned reg_size = rd.SizeInBits(); in LogicalImmediate()
2321 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
2322 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) | in LogicalImmediate()
2348 void Assembler::DataProcessing1Source(const Register& rd, in DataProcessing1Source() argument
2351 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in DataProcessing1Source()
2352 Emit(SF(rn) | op | Rn(rn) | Rd(rd)); in DataProcessing1Source()
2383 void Assembler::EmitShift(const Register& rd, in EmitShift() argument
2389 lsl(rd, rn, shift_amount); in EmitShift()
2392 lsr(rd, rn, shift_amount); in EmitShift()
2395 asr(rd, rn, shift_amount); in EmitShift()
2398 ror(rd, rn, shift_amount); in EmitShift()
2406 void Assembler::EmitExtendShift(const Register& rd, in EmitExtendShift() argument
2410 DCHECK(rd.SizeInBits() >= rn.SizeInBits()); in EmitExtendShift()
2411 unsigned reg_size = rd.SizeInBits(); in EmitExtendShift()
2413 Register rn_ = Register::Create(rn.code(), rd.SizeInBits()); in EmitExtendShift()
2423 case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
2426 case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break; in EmitExtendShift()
2431 lsl(rd, rn_, left_shift); in EmitExtendShift()
2438 lsl(rd, rn_, left_shift); in EmitExtendShift()
2443 void Assembler::DataProcShiftedRegister(const Register& rd, in DataProcShiftedRegister() argument
2451 Emit(SF(rd) | op | Flags(S) | in DataProcShiftedRegister()
2453 Rm(operand.reg()) | Rn(rn) | Rd(rd)); in DataProcShiftedRegister()
2457 void Assembler::DataProcExtendedRegister(const Register& rd, in DataProcExtendedRegister() argument
2463 Instr dest_reg = (S == SetFlags) ? Rd(rd) : RdSP(rd); in DataProcExtendedRegister()
2464 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | in DataProcExtendedRegister()
3132 Register rd = Register::XRegFromCode(rd_code); in PatchAdrFar() local
3135 adr(rd, target_offset & 0xFFFF); in PatchAdrFar()
3139 add(rd, rd, scratch); in PatchAdrFar()