1 /*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "code_generator_mips.h"
18
19 #include "arch/mips/entrypoints_direct_mips.h"
20 #include "arch/mips/instruction_set_features_mips.h"
21 #include "art_method.h"
22 #include "code_generator_utils.h"
23 #include "entrypoints/quick/quick_entrypoints.h"
24 #include "entrypoints/quick/quick_entrypoints_enum.h"
25 #include "gc/accounting/card_table.h"
26 #include "intrinsics.h"
27 #include "intrinsics_mips.h"
28 #include "mirror/array-inl.h"
29 #include "mirror/class-inl.h"
30 #include "offsets.h"
31 #include "thread.h"
32 #include "utils/assembler.h"
33 #include "utils/mips/assembler_mips.h"
34 #include "utils/stack_checks.h"
35
36 namespace art {
37 namespace mips {
38
39 static constexpr int kCurrentMethodStackOffset = 0;
40 static constexpr Register kMethodRegisterArgument = A0;
41
MipsReturnLocation(Primitive::Type return_type)42 Location MipsReturnLocation(Primitive::Type return_type) {
43 switch (return_type) {
44 case Primitive::kPrimBoolean:
45 case Primitive::kPrimByte:
46 case Primitive::kPrimChar:
47 case Primitive::kPrimShort:
48 case Primitive::kPrimInt:
49 case Primitive::kPrimNot:
50 return Location::RegisterLocation(V0);
51
52 case Primitive::kPrimLong:
53 return Location::RegisterPairLocation(V0, V1);
54
55 case Primitive::kPrimFloat:
56 case Primitive::kPrimDouble:
57 return Location::FpuRegisterLocation(F0);
58
59 case Primitive::kPrimVoid:
60 return Location();
61 }
62 UNREACHABLE();
63 }
64
GetReturnLocation(Primitive::Type type) const65 Location InvokeDexCallingConventionVisitorMIPS::GetReturnLocation(Primitive::Type type) const {
66 return MipsReturnLocation(type);
67 }
68
GetMethodLocation() const69 Location InvokeDexCallingConventionVisitorMIPS::GetMethodLocation() const {
70 return Location::RegisterLocation(kMethodRegisterArgument);
71 }
72
GetNextLocation(Primitive::Type type)73 Location InvokeDexCallingConventionVisitorMIPS::GetNextLocation(Primitive::Type type) {
74 Location next_location;
75
76 switch (type) {
77 case Primitive::kPrimBoolean:
78 case Primitive::kPrimByte:
79 case Primitive::kPrimChar:
80 case Primitive::kPrimShort:
81 case Primitive::kPrimInt:
82 case Primitive::kPrimNot: {
83 uint32_t gp_index = gp_index_++;
84 if (gp_index < calling_convention.GetNumberOfRegisters()) {
85 next_location = Location::RegisterLocation(calling_convention.GetRegisterAt(gp_index));
86 } else {
87 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
88 next_location = Location::StackSlot(stack_offset);
89 }
90 break;
91 }
92
93 case Primitive::kPrimLong: {
94 uint32_t gp_index = gp_index_;
95 gp_index_ += 2;
96 if (gp_index + 1 < calling_convention.GetNumberOfRegisters()) {
97 if (calling_convention.GetRegisterAt(gp_index) == A1) {
98 gp_index_++; // Skip A1, and use A2_A3 instead.
99 gp_index++;
100 }
101 Register low_even = calling_convention.GetRegisterAt(gp_index);
102 Register high_odd = calling_convention.GetRegisterAt(gp_index + 1);
103 DCHECK_EQ(low_even + 1, high_odd);
104 next_location = Location::RegisterPairLocation(low_even, high_odd);
105 } else {
106 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
107 next_location = Location::DoubleStackSlot(stack_offset);
108 }
109 break;
110 }
111
112 // Note: both float and double types are stored in even FPU registers. On 32 bit FPU, double
113 // will take up the even/odd pair, while floats are stored in even regs only.
114 // On 64 bit FPU, both double and float are stored in even registers only.
115 case Primitive::kPrimFloat:
116 case Primitive::kPrimDouble: {
117 uint32_t float_index = float_index_++;
118 if (float_index < calling_convention.GetNumberOfFpuRegisters()) {
119 next_location = Location::FpuRegisterLocation(
120 calling_convention.GetFpuRegisterAt(float_index));
121 } else {
122 size_t stack_offset = calling_convention.GetStackOffsetOf(stack_index_);
123 next_location = Primitive::Is64BitType(type) ? Location::DoubleStackSlot(stack_offset)
124 : Location::StackSlot(stack_offset);
125 }
126 break;
127 }
128
129 case Primitive::kPrimVoid:
130 LOG(FATAL) << "Unexpected parameter type " << type;
131 break;
132 }
133
134 // Space on the stack is reserved for all arguments.
135 stack_index_ += Primitive::Is64BitType(type) ? 2 : 1;
136
137 return next_location;
138 }
139
GetReturnLocation(Primitive::Type type)140 Location InvokeRuntimeCallingConvention::GetReturnLocation(Primitive::Type type) {
141 return MipsReturnLocation(type);
142 }
143
144 #define __ down_cast<CodeGeneratorMIPS*>(codegen)->GetAssembler()->
145 #define QUICK_ENTRY_POINT(x) QUICK_ENTRYPOINT_OFFSET(kMipsWordSize, x).Int32Value()
146
147 class BoundsCheckSlowPathMIPS : public SlowPathCodeMIPS {
148 public:
BoundsCheckSlowPathMIPS(HBoundsCheck * instruction)149 explicit BoundsCheckSlowPathMIPS(HBoundsCheck* instruction) : SlowPathCodeMIPS(instruction) {}
150
EmitNativeCode(CodeGenerator * codegen)151 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
152 LocationSummary* locations = instruction_->GetLocations();
153 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
154 __ Bind(GetEntryLabel());
155 if (instruction_->CanThrowIntoCatchBlock()) {
156 // Live registers will be restored in the catch block if caught.
157 SaveLiveRegisters(codegen, instruction_->GetLocations());
158 }
159 // We're moving two locations to locations that could overlap, so we need a parallel
160 // move resolver.
161 InvokeRuntimeCallingConvention calling_convention;
162 codegen->EmitParallelMoves(locations->InAt(0),
163 Location::RegisterLocation(calling_convention.GetRegisterAt(0)),
164 Primitive::kPrimInt,
165 locations->InAt(1),
166 Location::RegisterLocation(calling_convention.GetRegisterAt(1)),
167 Primitive::kPrimInt);
168 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowArrayBounds),
169 instruction_,
170 instruction_->GetDexPc(),
171 this,
172 IsDirectEntrypoint(kQuickThrowArrayBounds));
173 CheckEntrypointTypes<kQuickThrowArrayBounds, void, int32_t, int32_t>();
174 }
175
IsFatal() const176 bool IsFatal() const OVERRIDE { return true; }
177
GetDescription() const178 const char* GetDescription() const OVERRIDE { return "BoundsCheckSlowPathMIPS"; }
179
180 private:
181 DISALLOW_COPY_AND_ASSIGN(BoundsCheckSlowPathMIPS);
182 };
183
184 class DivZeroCheckSlowPathMIPS : public SlowPathCodeMIPS {
185 public:
DivZeroCheckSlowPathMIPS(HDivZeroCheck * instruction)186 explicit DivZeroCheckSlowPathMIPS(HDivZeroCheck* instruction) : SlowPathCodeMIPS(instruction) {}
187
EmitNativeCode(CodeGenerator * codegen)188 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
189 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
190 __ Bind(GetEntryLabel());
191 if (instruction_->CanThrowIntoCatchBlock()) {
192 // Live registers will be restored in the catch block if caught.
193 SaveLiveRegisters(codegen, instruction_->GetLocations());
194 }
195 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowDivZero),
196 instruction_,
197 instruction_->GetDexPc(),
198 this,
199 IsDirectEntrypoint(kQuickThrowDivZero));
200 CheckEntrypointTypes<kQuickThrowDivZero, void, void>();
201 }
202
IsFatal() const203 bool IsFatal() const OVERRIDE { return true; }
204
GetDescription() const205 const char* GetDescription() const OVERRIDE { return "DivZeroCheckSlowPathMIPS"; }
206
207 private:
208 DISALLOW_COPY_AND_ASSIGN(DivZeroCheckSlowPathMIPS);
209 };
210
211 class LoadClassSlowPathMIPS : public SlowPathCodeMIPS {
212 public:
LoadClassSlowPathMIPS(HLoadClass * cls,HInstruction * at,uint32_t dex_pc,bool do_clinit)213 LoadClassSlowPathMIPS(HLoadClass* cls,
214 HInstruction* at,
215 uint32_t dex_pc,
216 bool do_clinit)
217 : SlowPathCodeMIPS(at), cls_(cls), at_(at), dex_pc_(dex_pc), do_clinit_(do_clinit) {
218 DCHECK(at->IsLoadClass() || at->IsClinitCheck());
219 }
220
EmitNativeCode(CodeGenerator * codegen)221 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
222 LocationSummary* locations = at_->GetLocations();
223 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
224
225 __ Bind(GetEntryLabel());
226 SaveLiveRegisters(codegen, locations);
227
228 InvokeRuntimeCallingConvention calling_convention;
229 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
230
231 int32_t entry_point_offset = do_clinit_ ? QUICK_ENTRY_POINT(pInitializeStaticStorage)
232 : QUICK_ENTRY_POINT(pInitializeType);
233 bool direct = do_clinit_ ? IsDirectEntrypoint(kQuickInitializeStaticStorage)
234 : IsDirectEntrypoint(kQuickInitializeType);
235
236 mips_codegen->InvokeRuntime(entry_point_offset, at_, dex_pc_, this, direct);
237 if (do_clinit_) {
238 CheckEntrypointTypes<kQuickInitializeStaticStorage, void*, uint32_t>();
239 } else {
240 CheckEntrypointTypes<kQuickInitializeType, void*, uint32_t>();
241 }
242
243 // Move the class to the desired location.
244 Location out = locations->Out();
245 if (out.IsValid()) {
246 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
247 Primitive::Type type = at_->GetType();
248 mips_codegen->MoveLocation(out, calling_convention.GetReturnLocation(type), type);
249 }
250
251 RestoreLiveRegisters(codegen, locations);
252 __ B(GetExitLabel());
253 }
254
GetDescription() const255 const char* GetDescription() const OVERRIDE { return "LoadClassSlowPathMIPS"; }
256
257 private:
258 // The class this slow path will load.
259 HLoadClass* const cls_;
260
261 // The instruction where this slow path is happening.
262 // (Might be the load class or an initialization check).
263 HInstruction* const at_;
264
265 // The dex PC of `at_`.
266 const uint32_t dex_pc_;
267
268 // Whether to initialize the class.
269 const bool do_clinit_;
270
271 DISALLOW_COPY_AND_ASSIGN(LoadClassSlowPathMIPS);
272 };
273
274 class LoadStringSlowPathMIPS : public SlowPathCodeMIPS {
275 public:
LoadStringSlowPathMIPS(HLoadString * instruction)276 explicit LoadStringSlowPathMIPS(HLoadString* instruction) : SlowPathCodeMIPS(instruction) {}
277
EmitNativeCode(CodeGenerator * codegen)278 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
279 LocationSummary* locations = instruction_->GetLocations();
280 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
281 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
282
283 __ Bind(GetEntryLabel());
284 SaveLiveRegisters(codegen, locations);
285
286 InvokeRuntimeCallingConvention calling_convention;
287 const uint32_t string_index = instruction_->AsLoadString()->GetStringIndex();
288 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index);
289 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pResolveString),
290 instruction_,
291 instruction_->GetDexPc(),
292 this,
293 IsDirectEntrypoint(kQuickResolveString));
294 CheckEntrypointTypes<kQuickResolveString, void*, uint32_t>();
295 Primitive::Type type = instruction_->GetType();
296 mips_codegen->MoveLocation(locations->Out(),
297 calling_convention.GetReturnLocation(type),
298 type);
299
300 RestoreLiveRegisters(codegen, locations);
301 __ B(GetExitLabel());
302 }
303
GetDescription() const304 const char* GetDescription() const OVERRIDE { return "LoadStringSlowPathMIPS"; }
305
306 private:
307 DISALLOW_COPY_AND_ASSIGN(LoadStringSlowPathMIPS);
308 };
309
310 class NullCheckSlowPathMIPS : public SlowPathCodeMIPS {
311 public:
NullCheckSlowPathMIPS(HNullCheck * instr)312 explicit NullCheckSlowPathMIPS(HNullCheck* instr) : SlowPathCodeMIPS(instr) {}
313
EmitNativeCode(CodeGenerator * codegen)314 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
315 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
316 __ Bind(GetEntryLabel());
317 if (instruction_->CanThrowIntoCatchBlock()) {
318 // Live registers will be restored in the catch block if caught.
319 SaveLiveRegisters(codegen, instruction_->GetLocations());
320 }
321 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pThrowNullPointer),
322 instruction_,
323 instruction_->GetDexPc(),
324 this,
325 IsDirectEntrypoint(kQuickThrowNullPointer));
326 CheckEntrypointTypes<kQuickThrowNullPointer, void, void>();
327 }
328
IsFatal() const329 bool IsFatal() const OVERRIDE { return true; }
330
GetDescription() const331 const char* GetDescription() const OVERRIDE { return "NullCheckSlowPathMIPS"; }
332
333 private:
334 DISALLOW_COPY_AND_ASSIGN(NullCheckSlowPathMIPS);
335 };
336
337 class SuspendCheckSlowPathMIPS : public SlowPathCodeMIPS {
338 public:
SuspendCheckSlowPathMIPS(HSuspendCheck * instruction,HBasicBlock * successor)339 SuspendCheckSlowPathMIPS(HSuspendCheck* instruction, HBasicBlock* successor)
340 : SlowPathCodeMIPS(instruction), successor_(successor) {}
341
EmitNativeCode(CodeGenerator * codegen)342 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
343 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
344 __ Bind(GetEntryLabel());
345 SaveLiveRegisters(codegen, instruction_->GetLocations());
346 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pTestSuspend),
347 instruction_,
348 instruction_->GetDexPc(),
349 this,
350 IsDirectEntrypoint(kQuickTestSuspend));
351 CheckEntrypointTypes<kQuickTestSuspend, void, void>();
352 RestoreLiveRegisters(codegen, instruction_->GetLocations());
353 if (successor_ == nullptr) {
354 __ B(GetReturnLabel());
355 } else {
356 __ B(mips_codegen->GetLabelOf(successor_));
357 }
358 }
359
GetReturnLabel()360 MipsLabel* GetReturnLabel() {
361 DCHECK(successor_ == nullptr);
362 return &return_label_;
363 }
364
GetDescription() const365 const char* GetDescription() const OVERRIDE { return "SuspendCheckSlowPathMIPS"; }
366
367 private:
368 // If not null, the block to branch to after the suspend check.
369 HBasicBlock* const successor_;
370
371 // If `successor_` is null, the label to branch to after the suspend check.
372 MipsLabel return_label_;
373
374 DISALLOW_COPY_AND_ASSIGN(SuspendCheckSlowPathMIPS);
375 };
376
377 class TypeCheckSlowPathMIPS : public SlowPathCodeMIPS {
378 public:
TypeCheckSlowPathMIPS(HInstruction * instruction)379 explicit TypeCheckSlowPathMIPS(HInstruction* instruction) : SlowPathCodeMIPS(instruction) {}
380
EmitNativeCode(CodeGenerator * codegen)381 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
382 LocationSummary* locations = instruction_->GetLocations();
383 Location object_class = instruction_->IsCheckCast() ? locations->GetTemp(0) : locations->Out();
384 uint32_t dex_pc = instruction_->GetDexPc();
385 DCHECK(instruction_->IsCheckCast()
386 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
387 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
388
389 __ Bind(GetEntryLabel());
390 SaveLiveRegisters(codegen, locations);
391
392 // We're moving two locations to locations that could overlap, so we need a parallel
393 // move resolver.
394 InvokeRuntimeCallingConvention calling_convention;
395 codegen->EmitParallelMoves(locations->InAt(1),
396 Location::RegisterLocation(calling_convention.GetRegisterAt(0)),
397 Primitive::kPrimNot,
398 object_class,
399 Location::RegisterLocation(calling_convention.GetRegisterAt(1)),
400 Primitive::kPrimNot);
401
402 if (instruction_->IsInstanceOf()) {
403 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pInstanceofNonTrivial),
404 instruction_,
405 dex_pc,
406 this,
407 IsDirectEntrypoint(kQuickInstanceofNonTrivial));
408 CheckEntrypointTypes<
409 kQuickInstanceofNonTrivial, uint32_t, const mirror::Class*, const mirror::Class*>();
410 Primitive::Type ret_type = instruction_->GetType();
411 Location ret_loc = calling_convention.GetReturnLocation(ret_type);
412 mips_codegen->MoveLocation(locations->Out(), ret_loc, ret_type);
413 } else {
414 DCHECK(instruction_->IsCheckCast());
415 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pCheckCast),
416 instruction_,
417 dex_pc,
418 this,
419 IsDirectEntrypoint(kQuickCheckCast));
420 CheckEntrypointTypes<kQuickCheckCast, void, const mirror::Class*, const mirror::Class*>();
421 }
422
423 RestoreLiveRegisters(codegen, locations);
424 __ B(GetExitLabel());
425 }
426
GetDescription() const427 const char* GetDescription() const OVERRIDE { return "TypeCheckSlowPathMIPS"; }
428
429 private:
430 DISALLOW_COPY_AND_ASSIGN(TypeCheckSlowPathMIPS);
431 };
432
433 class DeoptimizationSlowPathMIPS : public SlowPathCodeMIPS {
434 public:
DeoptimizationSlowPathMIPS(HDeoptimize * instruction)435 explicit DeoptimizationSlowPathMIPS(HDeoptimize* instruction)
436 : SlowPathCodeMIPS(instruction) {}
437
EmitNativeCode(CodeGenerator * codegen)438 void EmitNativeCode(CodeGenerator* codegen) OVERRIDE {
439 CodeGeneratorMIPS* mips_codegen = down_cast<CodeGeneratorMIPS*>(codegen);
440 __ Bind(GetEntryLabel());
441 SaveLiveRegisters(codegen, instruction_->GetLocations());
442 mips_codegen->InvokeRuntime(QUICK_ENTRY_POINT(pDeoptimize),
443 instruction_,
444 instruction_->GetDexPc(),
445 this,
446 IsDirectEntrypoint(kQuickDeoptimize));
447 CheckEntrypointTypes<kQuickDeoptimize, void, void>();
448 }
449
GetDescription() const450 const char* GetDescription() const OVERRIDE { return "DeoptimizationSlowPathMIPS"; }
451
452 private:
453 DISALLOW_COPY_AND_ASSIGN(DeoptimizationSlowPathMIPS);
454 };
455
CodeGeneratorMIPS(HGraph * graph,const MipsInstructionSetFeatures & isa_features,const CompilerOptions & compiler_options,OptimizingCompilerStats * stats)456 CodeGeneratorMIPS::CodeGeneratorMIPS(HGraph* graph,
457 const MipsInstructionSetFeatures& isa_features,
458 const CompilerOptions& compiler_options,
459 OptimizingCompilerStats* stats)
460 : CodeGenerator(graph,
461 kNumberOfCoreRegisters,
462 kNumberOfFRegisters,
463 kNumberOfRegisterPairs,
464 ComputeRegisterMask(reinterpret_cast<const int*>(kCoreCalleeSaves),
465 arraysize(kCoreCalleeSaves)),
466 ComputeRegisterMask(reinterpret_cast<const int*>(kFpuCalleeSaves),
467 arraysize(kFpuCalleeSaves)),
468 compiler_options,
469 stats),
470 block_labels_(nullptr),
471 location_builder_(graph, this),
472 instruction_visitor_(graph, this),
473 move_resolver_(graph->GetArena(), this),
474 assembler_(graph->GetArena(), &isa_features),
475 isa_features_(isa_features) {
476 // Save RA (containing the return address) to mimic Quick.
477 AddAllocatedRegister(Location::RegisterLocation(RA));
478 }
479
480 #undef __
481 #define __ down_cast<MipsAssembler*>(GetAssembler())->
482 #define QUICK_ENTRY_POINT(x) QUICK_ENTRYPOINT_OFFSET(kMipsWordSize, x).Int32Value()
483
Finalize(CodeAllocator * allocator)484 void CodeGeneratorMIPS::Finalize(CodeAllocator* allocator) {
485 // Ensure that we fix up branches.
486 __ FinalizeCode();
487
488 // Adjust native pc offsets in stack maps.
489 for (size_t i = 0, num = stack_map_stream_.GetNumberOfStackMaps(); i != num; ++i) {
490 uint32_t old_position = stack_map_stream_.GetStackMap(i).native_pc_offset;
491 uint32_t new_position = __ GetAdjustedPosition(old_position);
492 DCHECK_GE(new_position, old_position);
493 stack_map_stream_.SetStackMapNativePcOffset(i, new_position);
494 }
495
496 // Adjust pc offsets for the disassembly information.
497 if (disasm_info_ != nullptr) {
498 GeneratedCodeInterval* frame_entry_interval = disasm_info_->GetFrameEntryInterval();
499 frame_entry_interval->start = __ GetAdjustedPosition(frame_entry_interval->start);
500 frame_entry_interval->end = __ GetAdjustedPosition(frame_entry_interval->end);
501 for (auto& it : *disasm_info_->GetInstructionIntervals()) {
502 it.second.start = __ GetAdjustedPosition(it.second.start);
503 it.second.end = __ GetAdjustedPosition(it.second.end);
504 }
505 for (auto& it : *disasm_info_->GetSlowPathIntervals()) {
506 it.code_interval.start = __ GetAdjustedPosition(it.code_interval.start);
507 it.code_interval.end = __ GetAdjustedPosition(it.code_interval.end);
508 }
509 }
510
511 CodeGenerator::Finalize(allocator);
512 }
513
GetAssembler() const514 MipsAssembler* ParallelMoveResolverMIPS::GetAssembler() const {
515 return codegen_->GetAssembler();
516 }
517
EmitMove(size_t index)518 void ParallelMoveResolverMIPS::EmitMove(size_t index) {
519 DCHECK_LT(index, moves_.size());
520 MoveOperands* move = moves_[index];
521 codegen_->MoveLocation(move->GetDestination(), move->GetSource(), move->GetType());
522 }
523
EmitSwap(size_t index)524 void ParallelMoveResolverMIPS::EmitSwap(size_t index) {
525 DCHECK_LT(index, moves_.size());
526 MoveOperands* move = moves_[index];
527 Primitive::Type type = move->GetType();
528 Location loc1 = move->GetDestination();
529 Location loc2 = move->GetSource();
530
531 DCHECK(!loc1.IsConstant());
532 DCHECK(!loc2.IsConstant());
533
534 if (loc1.Equals(loc2)) {
535 return;
536 }
537
538 if (loc1.IsRegister() && loc2.IsRegister()) {
539 // Swap 2 GPRs.
540 Register r1 = loc1.AsRegister<Register>();
541 Register r2 = loc2.AsRegister<Register>();
542 __ Move(TMP, r2);
543 __ Move(r2, r1);
544 __ Move(r1, TMP);
545 } else if (loc1.IsFpuRegister() && loc2.IsFpuRegister()) {
546 FRegister f1 = loc1.AsFpuRegister<FRegister>();
547 FRegister f2 = loc2.AsFpuRegister<FRegister>();
548 if (type == Primitive::kPrimFloat) {
549 __ MovS(FTMP, f2);
550 __ MovS(f2, f1);
551 __ MovS(f1, FTMP);
552 } else {
553 DCHECK_EQ(type, Primitive::kPrimDouble);
554 __ MovD(FTMP, f2);
555 __ MovD(f2, f1);
556 __ MovD(f1, FTMP);
557 }
558 } else if ((loc1.IsRegister() && loc2.IsFpuRegister()) ||
559 (loc1.IsFpuRegister() && loc2.IsRegister())) {
560 // Swap FPR and GPR.
561 DCHECK_EQ(type, Primitive::kPrimFloat); // Can only swap a float.
562 FRegister f1 = loc1.IsFpuRegister() ? loc1.AsFpuRegister<FRegister>()
563 : loc2.AsFpuRegister<FRegister>();
564 Register r2 = loc1.IsRegister() ? loc1.AsRegister<Register>()
565 : loc2.AsRegister<Register>();
566 __ Move(TMP, r2);
567 __ Mfc1(r2, f1);
568 __ Mtc1(TMP, f1);
569 } else if (loc1.IsRegisterPair() && loc2.IsRegisterPair()) {
570 // Swap 2 GPR register pairs.
571 Register r1 = loc1.AsRegisterPairLow<Register>();
572 Register r2 = loc2.AsRegisterPairLow<Register>();
573 __ Move(TMP, r2);
574 __ Move(r2, r1);
575 __ Move(r1, TMP);
576 r1 = loc1.AsRegisterPairHigh<Register>();
577 r2 = loc2.AsRegisterPairHigh<Register>();
578 __ Move(TMP, r2);
579 __ Move(r2, r1);
580 __ Move(r1, TMP);
581 } else if ((loc1.IsRegisterPair() && loc2.IsFpuRegister()) ||
582 (loc1.IsFpuRegister() && loc2.IsRegisterPair())) {
583 // Swap FPR and GPR register pair.
584 DCHECK_EQ(type, Primitive::kPrimDouble);
585 FRegister f1 = loc1.IsFpuRegister() ? loc1.AsFpuRegister<FRegister>()
586 : loc2.AsFpuRegister<FRegister>();
587 Register r2_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>()
588 : loc2.AsRegisterPairLow<Register>();
589 Register r2_h = loc1.IsRegisterPair() ? loc1.AsRegisterPairHigh<Register>()
590 : loc2.AsRegisterPairHigh<Register>();
591 // Use 2 temporary registers because we can't first swap the low 32 bits of an FPR and
592 // then swap the high 32 bits of the same FPR. mtc1 makes the high 32 bits of an FPR
593 // unpredictable and the following mfch1 will fail.
594 __ Mfc1(TMP, f1);
595 __ MoveFromFpuHigh(AT, f1);
596 __ Mtc1(r2_l, f1);
597 __ MoveToFpuHigh(r2_h, f1);
598 __ Move(r2_l, TMP);
599 __ Move(r2_h, AT);
600 } else if (loc1.IsStackSlot() && loc2.IsStackSlot()) {
601 Exchange(loc1.GetStackIndex(), loc2.GetStackIndex(), /* double_slot */ false);
602 } else if (loc1.IsDoubleStackSlot() && loc2.IsDoubleStackSlot()) {
603 Exchange(loc1.GetStackIndex(), loc2.GetStackIndex(), /* double_slot */ true);
604 } else if ((loc1.IsRegister() && loc2.IsStackSlot()) ||
605 (loc1.IsStackSlot() && loc2.IsRegister())) {
606 Register reg = loc1.IsRegister() ? loc1.AsRegister<Register>()
607 : loc2.AsRegister<Register>();
608 intptr_t offset = loc1.IsStackSlot() ? loc1.GetStackIndex()
609 : loc2.GetStackIndex();
610 __ Move(TMP, reg);
611 __ LoadFromOffset(kLoadWord, reg, SP, offset);
612 __ StoreToOffset(kStoreWord, TMP, SP, offset);
613 } else if ((loc1.IsRegisterPair() && loc2.IsDoubleStackSlot()) ||
614 (loc1.IsDoubleStackSlot() && loc2.IsRegisterPair())) {
615 Register reg_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>()
616 : loc2.AsRegisterPairLow<Register>();
617 Register reg_h = loc1.IsRegisterPair() ? loc1.AsRegisterPairHigh<Register>()
618 : loc2.AsRegisterPairHigh<Register>();
619 intptr_t offset_l = loc1.IsDoubleStackSlot() ? loc1.GetStackIndex()
620 : loc2.GetStackIndex();
621 intptr_t offset_h = loc1.IsDoubleStackSlot() ? loc1.GetHighStackIndex(kMipsWordSize)
622 : loc2.GetHighStackIndex(kMipsWordSize);
623 __ Move(TMP, reg_l);
624 __ LoadFromOffset(kLoadWord, reg_l, SP, offset_l);
625 __ StoreToOffset(kStoreWord, TMP, SP, offset_l);
626 __ Move(TMP, reg_h);
627 __ LoadFromOffset(kLoadWord, reg_h, SP, offset_h);
628 __ StoreToOffset(kStoreWord, TMP, SP, offset_h);
629 } else {
630 LOG(FATAL) << "Swap between " << loc1 << " and " << loc2 << " is unsupported";
631 }
632 }
633
RestoreScratch(int reg)634 void ParallelMoveResolverMIPS::RestoreScratch(int reg) {
635 __ Pop(static_cast<Register>(reg));
636 }
637
SpillScratch(int reg)638 void ParallelMoveResolverMIPS::SpillScratch(int reg) {
639 __ Push(static_cast<Register>(reg));
640 }
641
Exchange(int index1,int index2,bool double_slot)642 void ParallelMoveResolverMIPS::Exchange(int index1, int index2, bool double_slot) {
643 // Allocate a scratch register other than TMP, if available.
644 // Else, spill V0 (arbitrary choice) and use it as a scratch register (it will be
645 // automatically unspilled when the scratch scope object is destroyed).
646 ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters());
647 // If V0 spills onto the stack, SP-relative offsets need to be adjusted.
648 int stack_offset = ensure_scratch.IsSpilled() ? kMipsWordSize : 0;
649 for (int i = 0; i <= (double_slot ? 1 : 0); i++, stack_offset += kMipsWordSize) {
650 __ LoadFromOffset(kLoadWord,
651 Register(ensure_scratch.GetRegister()),
652 SP,
653 index1 + stack_offset);
654 __ LoadFromOffset(kLoadWord,
655 TMP,
656 SP,
657 index2 + stack_offset);
658 __ StoreToOffset(kStoreWord,
659 Register(ensure_scratch.GetRegister()),
660 SP,
661 index2 + stack_offset);
662 __ StoreToOffset(kStoreWord, TMP, SP, index1 + stack_offset);
663 }
664 }
665
DWARFReg(Register reg)666 static dwarf::Reg DWARFReg(Register reg) {
667 return dwarf::Reg::MipsCore(static_cast<int>(reg));
668 }
669
670 // TODO: mapping of floating-point registers to DWARF.
671
GenerateFrameEntry()672 void CodeGeneratorMIPS::GenerateFrameEntry() {
673 __ Bind(&frame_entry_label_);
674
675 bool do_overflow_check = FrameNeedsStackCheck(GetFrameSize(), kMips) || !IsLeafMethod();
676
677 if (do_overflow_check) {
678 __ LoadFromOffset(kLoadWord,
679 ZERO,
680 SP,
681 -static_cast<int32_t>(GetStackOverflowReservedBytes(kMips)));
682 RecordPcInfo(nullptr, 0);
683 }
684
685 if (HasEmptyFrame()) {
686 return;
687 }
688
689 // Make sure the frame size isn't unreasonably large.
690 if (GetFrameSize() > GetStackOverflowReservedBytes(kMips)) {
691 LOG(FATAL) << "Stack frame larger than " << GetStackOverflowReservedBytes(kMips) << " bytes";
692 }
693
694 // Spill callee-saved registers.
695 // Note that their cumulative size is small and they can be indexed using
696 // 16-bit offsets.
697
698 // TODO: increment/decrement SP in one step instead of two or remove this comment.
699
700 uint32_t ofs = FrameEntrySpillSize();
701 bool unaligned_float = ofs & 0x7;
702 bool fpu_32bit = isa_features_.Is32BitFloatingPoint();
703 __ IncreaseFrameSize(ofs);
704
705 for (int i = arraysize(kCoreCalleeSaves) - 1; i >= 0; --i) {
706 Register reg = kCoreCalleeSaves[i];
707 if (allocated_registers_.ContainsCoreRegister(reg)) {
708 ofs -= kMipsWordSize;
709 __ Sw(reg, SP, ofs);
710 __ cfi().RelOffset(DWARFReg(reg), ofs);
711 }
712 }
713
714 for (int i = arraysize(kFpuCalleeSaves) - 1; i >= 0; --i) {
715 FRegister reg = kFpuCalleeSaves[i];
716 if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
717 ofs -= kMipsDoublewordSize;
718 // TODO: Change the frame to avoid unaligned accesses for fpu registers.
719 if (unaligned_float) {
720 if (fpu_32bit) {
721 __ Swc1(reg, SP, ofs);
722 __ Swc1(static_cast<FRegister>(reg + 1), SP, ofs + 4);
723 } else {
724 __ Mfhc1(TMP, reg);
725 __ Swc1(reg, SP, ofs);
726 __ Sw(TMP, SP, ofs + 4);
727 }
728 } else {
729 __ Sdc1(reg, SP, ofs);
730 }
731 // TODO: __ cfi().RelOffset(DWARFReg(reg), ofs);
732 }
733 }
734
735 // Allocate the rest of the frame and store the current method pointer
736 // at its end.
737
738 __ IncreaseFrameSize(GetFrameSize() - FrameEntrySpillSize());
739
740 static_assert(IsInt<16>(kCurrentMethodStackOffset),
741 "kCurrentMethodStackOffset must fit into int16_t");
742 __ Sw(kMethodRegisterArgument, SP, kCurrentMethodStackOffset);
743 }
744
GenerateFrameExit()745 void CodeGeneratorMIPS::GenerateFrameExit() {
746 __ cfi().RememberState();
747
748 if (!HasEmptyFrame()) {
749 // Deallocate the rest of the frame.
750
751 __ DecreaseFrameSize(GetFrameSize() - FrameEntrySpillSize());
752
753 // Restore callee-saved registers.
754 // Note that their cumulative size is small and they can be indexed using
755 // 16-bit offsets.
756
757 // TODO: increment/decrement SP in one step instead of two or remove this comment.
758
759 uint32_t ofs = 0;
760 bool unaligned_float = FrameEntrySpillSize() & 0x7;
761 bool fpu_32bit = isa_features_.Is32BitFloatingPoint();
762
763 for (size_t i = 0; i < arraysize(kFpuCalleeSaves); ++i) {
764 FRegister reg = kFpuCalleeSaves[i];
765 if (allocated_registers_.ContainsFloatingPointRegister(reg)) {
766 if (unaligned_float) {
767 if (fpu_32bit) {
768 __ Lwc1(reg, SP, ofs);
769 __ Lwc1(static_cast<FRegister>(reg + 1), SP, ofs + 4);
770 } else {
771 __ Lwc1(reg, SP, ofs);
772 __ Lw(TMP, SP, ofs + 4);
773 __ Mthc1(TMP, reg);
774 }
775 } else {
776 __ Ldc1(reg, SP, ofs);
777 }
778 ofs += kMipsDoublewordSize;
779 // TODO: __ cfi().Restore(DWARFReg(reg));
780 }
781 }
782
783 for (size_t i = 0; i < arraysize(kCoreCalleeSaves); ++i) {
784 Register reg = kCoreCalleeSaves[i];
785 if (allocated_registers_.ContainsCoreRegister(reg)) {
786 __ Lw(reg, SP, ofs);
787 ofs += kMipsWordSize;
788 __ cfi().Restore(DWARFReg(reg));
789 }
790 }
791
792 DCHECK_EQ(ofs, FrameEntrySpillSize());
793 __ DecreaseFrameSize(ofs);
794 }
795
796 __ Jr(RA);
797 __ Nop();
798
799 __ cfi().RestoreState();
800 __ cfi().DefCFAOffset(GetFrameSize());
801 }
802
Bind(HBasicBlock * block)803 void CodeGeneratorMIPS::Bind(HBasicBlock* block) {
804 __ Bind(GetLabelOf(block));
805 }
806
MoveLocation(Location dst,Location src,Primitive::Type dst_type)807 void CodeGeneratorMIPS::MoveLocation(Location dst, Location src, Primitive::Type dst_type) {
808 if (src.Equals(dst)) {
809 return;
810 }
811
812 if (src.IsConstant()) {
813 MoveConstant(dst, src.GetConstant());
814 } else {
815 if (Primitive::Is64BitType(dst_type)) {
816 Move64(dst, src);
817 } else {
818 Move32(dst, src);
819 }
820 }
821 }
822
Move32(Location destination,Location source)823 void CodeGeneratorMIPS::Move32(Location destination, Location source) {
824 if (source.Equals(destination)) {
825 return;
826 }
827
828 if (destination.IsRegister()) {
829 if (source.IsRegister()) {
830 __ Move(destination.AsRegister<Register>(), source.AsRegister<Register>());
831 } else if (source.IsFpuRegister()) {
832 __ Mfc1(destination.AsRegister<Register>(), source.AsFpuRegister<FRegister>());
833 } else {
834 DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
835 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), SP, source.GetStackIndex());
836 }
837 } else if (destination.IsFpuRegister()) {
838 if (source.IsRegister()) {
839 __ Mtc1(source.AsRegister<Register>(), destination.AsFpuRegister<FRegister>());
840 } else if (source.IsFpuRegister()) {
841 __ MovS(destination.AsFpuRegister<FRegister>(), source.AsFpuRegister<FRegister>());
842 } else {
843 DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
844 __ LoadSFromOffset(destination.AsFpuRegister<FRegister>(), SP, source.GetStackIndex());
845 }
846 } else {
847 DCHECK(destination.IsStackSlot()) << destination;
848 if (source.IsRegister()) {
849 __ StoreToOffset(kStoreWord, source.AsRegister<Register>(), SP, destination.GetStackIndex());
850 } else if (source.IsFpuRegister()) {
851 __ StoreSToOffset(source.AsFpuRegister<FRegister>(), SP, destination.GetStackIndex());
852 } else {
853 DCHECK(source.IsStackSlot()) << "Cannot move from " << source << " to " << destination;
854 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
855 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex());
856 }
857 }
858 }
859
Move64(Location destination,Location source)860 void CodeGeneratorMIPS::Move64(Location destination, Location source) {
861 if (source.Equals(destination)) {
862 return;
863 }
864
865 if (destination.IsRegisterPair()) {
866 if (source.IsRegisterPair()) {
867 __ Move(destination.AsRegisterPairHigh<Register>(), source.AsRegisterPairHigh<Register>());
868 __ Move(destination.AsRegisterPairLow<Register>(), source.AsRegisterPairLow<Register>());
869 } else if (source.IsFpuRegister()) {
870 Register dst_high = destination.AsRegisterPairHigh<Register>();
871 Register dst_low = destination.AsRegisterPairLow<Register>();
872 FRegister src = source.AsFpuRegister<FRegister>();
873 __ Mfc1(dst_low, src);
874 __ MoveFromFpuHigh(dst_high, src);
875 } else {
876 DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
877 int32_t off = source.GetStackIndex();
878 Register r = destination.AsRegisterPairLow<Register>();
879 __ LoadFromOffset(kLoadDoubleword, r, SP, off);
880 }
881 } else if (destination.IsFpuRegister()) {
882 if (source.IsRegisterPair()) {
883 FRegister dst = destination.AsFpuRegister<FRegister>();
884 Register src_high = source.AsRegisterPairHigh<Register>();
885 Register src_low = source.AsRegisterPairLow<Register>();
886 __ Mtc1(src_low, dst);
887 __ MoveToFpuHigh(src_high, dst);
888 } else if (source.IsFpuRegister()) {
889 __ MovD(destination.AsFpuRegister<FRegister>(), source.AsFpuRegister<FRegister>());
890 } else {
891 DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
892 __ LoadDFromOffset(destination.AsFpuRegister<FRegister>(), SP, source.GetStackIndex());
893 }
894 } else {
895 DCHECK(destination.IsDoubleStackSlot()) << destination;
896 int32_t off = destination.GetStackIndex();
897 if (source.IsRegisterPair()) {
898 __ StoreToOffset(kStoreDoubleword, source.AsRegisterPairLow<Register>(), SP, off);
899 } else if (source.IsFpuRegister()) {
900 __ StoreDToOffset(source.AsFpuRegister<FRegister>(), SP, off);
901 } else {
902 DCHECK(source.IsDoubleStackSlot()) << "Cannot move from " << source << " to " << destination;
903 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex());
904 __ StoreToOffset(kStoreWord, TMP, SP, off);
905 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex() + 4);
906 __ StoreToOffset(kStoreWord, TMP, SP, off + 4);
907 }
908 }
909 }
910
MoveConstant(Location destination,HConstant * c)911 void CodeGeneratorMIPS::MoveConstant(Location destination, HConstant* c) {
912 if (c->IsIntConstant() || c->IsNullConstant()) {
913 // Move 32 bit constant.
914 int32_t value = GetInt32ValueOf(c);
915 if (destination.IsRegister()) {
916 Register dst = destination.AsRegister<Register>();
917 __ LoadConst32(dst, value);
918 } else {
919 DCHECK(destination.IsStackSlot())
920 << "Cannot move " << c->DebugName() << " to " << destination;
921 __ StoreConst32ToOffset(value, SP, destination.GetStackIndex(), TMP);
922 }
923 } else if (c->IsLongConstant()) {
924 // Move 64 bit constant.
925 int64_t value = GetInt64ValueOf(c);
926 if (destination.IsRegisterPair()) {
927 Register r_h = destination.AsRegisterPairHigh<Register>();
928 Register r_l = destination.AsRegisterPairLow<Register>();
929 __ LoadConst64(r_h, r_l, value);
930 } else {
931 DCHECK(destination.IsDoubleStackSlot())
932 << "Cannot move " << c->DebugName() << " to " << destination;
933 __ StoreConst64ToOffset(value, SP, destination.GetStackIndex(), TMP);
934 }
935 } else if (c->IsFloatConstant()) {
936 // Move 32 bit float constant.
937 int32_t value = GetInt32ValueOf(c);
938 if (destination.IsFpuRegister()) {
939 __ LoadSConst32(destination.AsFpuRegister<FRegister>(), value, TMP);
940 } else {
941 DCHECK(destination.IsStackSlot())
942 << "Cannot move " << c->DebugName() << " to " << destination;
943 __ StoreConst32ToOffset(value, SP, destination.GetStackIndex(), TMP);
944 }
945 } else {
946 // Move 64 bit double constant.
947 DCHECK(c->IsDoubleConstant()) << c->DebugName();
948 int64_t value = GetInt64ValueOf(c);
949 if (destination.IsFpuRegister()) {
950 FRegister fd = destination.AsFpuRegister<FRegister>();
951 __ LoadDConst64(fd, value, TMP);
952 } else {
953 DCHECK(destination.IsDoubleStackSlot())
954 << "Cannot move " << c->DebugName() << " to " << destination;
955 __ StoreConst64ToOffset(value, SP, destination.GetStackIndex(), TMP);
956 }
957 }
958 }
959
MoveConstant(Location destination,int32_t value)960 void CodeGeneratorMIPS::MoveConstant(Location destination, int32_t value) {
961 DCHECK(destination.IsRegister());
962 Register dst = destination.AsRegister<Register>();
963 __ LoadConst32(dst, value);
964 }
965
AddLocationAsTemp(Location location,LocationSummary * locations)966 void CodeGeneratorMIPS::AddLocationAsTemp(Location location, LocationSummary* locations) {
967 if (location.IsRegister()) {
968 locations->AddTemp(location);
969 } else if (location.IsRegisterPair()) {
970 locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairLow<Register>()));
971 locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairHigh<Register>()));
972 } else {
973 UNIMPLEMENTED(FATAL) << "AddLocationAsTemp not implemented for location " << location;
974 }
975 }
976
MarkGCCard(Register object,Register value)977 void CodeGeneratorMIPS::MarkGCCard(Register object, Register value) {
978 MipsLabel done;
979 Register card = AT;
980 Register temp = TMP;
981 __ Beqz(value, &done);
982 __ LoadFromOffset(kLoadWord,
983 card,
984 TR,
985 Thread::CardTableOffset<kMipsWordSize>().Int32Value());
986 __ Srl(temp, object, gc::accounting::CardTable::kCardShift);
987 __ Addu(temp, card, temp);
988 __ Sb(card, temp, 0);
989 __ Bind(&done);
990 }
991
SetupBlockedRegisters() const992 void CodeGeneratorMIPS::SetupBlockedRegisters() const {
993 // Don't allocate the dalvik style register pair passing.
994 blocked_register_pairs_[A1_A2] = true;
995
996 // ZERO, K0, K1, GP, SP, RA are always reserved and can't be allocated.
997 blocked_core_registers_[ZERO] = true;
998 blocked_core_registers_[K0] = true;
999 blocked_core_registers_[K1] = true;
1000 blocked_core_registers_[GP] = true;
1001 blocked_core_registers_[SP] = true;
1002 blocked_core_registers_[RA] = true;
1003
1004 // AT and TMP(T8) are used as temporary/scratch registers
1005 // (similar to how AT is used by MIPS assemblers).
1006 blocked_core_registers_[AT] = true;
1007 blocked_core_registers_[TMP] = true;
1008 blocked_fpu_registers_[FTMP] = true;
1009
1010 // Reserve suspend and thread registers.
1011 blocked_core_registers_[S0] = true;
1012 blocked_core_registers_[TR] = true;
1013
1014 // Reserve T9 for function calls
1015 blocked_core_registers_[T9] = true;
1016
1017 // Reserve odd-numbered FPU registers.
1018 for (size_t i = 1; i < kNumberOfFRegisters; i += 2) {
1019 blocked_fpu_registers_[i] = true;
1020 }
1021
1022 UpdateBlockedPairRegisters();
1023 }
1024
UpdateBlockedPairRegisters() const1025 void CodeGeneratorMIPS::UpdateBlockedPairRegisters() const {
1026 for (int i = 0; i < kNumberOfRegisterPairs; i++) {
1027 MipsManagedRegister current =
1028 MipsManagedRegister::FromRegisterPair(static_cast<RegisterPair>(i));
1029 if (blocked_core_registers_[current.AsRegisterPairLow()]
1030 || blocked_core_registers_[current.AsRegisterPairHigh()]) {
1031 blocked_register_pairs_[i] = true;
1032 }
1033 }
1034 }
1035
SaveCoreRegister(size_t stack_index,uint32_t reg_id)1036 size_t CodeGeneratorMIPS::SaveCoreRegister(size_t stack_index, uint32_t reg_id) {
1037 __ StoreToOffset(kStoreWord, Register(reg_id), SP, stack_index);
1038 return kMipsWordSize;
1039 }
1040
RestoreCoreRegister(size_t stack_index,uint32_t reg_id)1041 size_t CodeGeneratorMIPS::RestoreCoreRegister(size_t stack_index, uint32_t reg_id) {
1042 __ LoadFromOffset(kLoadWord, Register(reg_id), SP, stack_index);
1043 return kMipsWordSize;
1044 }
1045
SaveFloatingPointRegister(size_t stack_index,uint32_t reg_id)1046 size_t CodeGeneratorMIPS::SaveFloatingPointRegister(size_t stack_index, uint32_t reg_id) {
1047 __ StoreDToOffset(FRegister(reg_id), SP, stack_index);
1048 return kMipsDoublewordSize;
1049 }
1050
RestoreFloatingPointRegister(size_t stack_index,uint32_t reg_id)1051 size_t CodeGeneratorMIPS::RestoreFloatingPointRegister(size_t stack_index, uint32_t reg_id) {
1052 __ LoadDFromOffset(FRegister(reg_id), SP, stack_index);
1053 return kMipsDoublewordSize;
1054 }
1055
DumpCoreRegister(std::ostream & stream,int reg) const1056 void CodeGeneratorMIPS::DumpCoreRegister(std::ostream& stream, int reg) const {
1057 stream << Register(reg);
1058 }
1059
DumpFloatingPointRegister(std::ostream & stream,int reg) const1060 void CodeGeneratorMIPS::DumpFloatingPointRegister(std::ostream& stream, int reg) const {
1061 stream << FRegister(reg);
1062 }
1063
InvokeRuntime(QuickEntrypointEnum entrypoint,HInstruction * instruction,uint32_t dex_pc,SlowPathCode * slow_path)1064 void CodeGeneratorMIPS::InvokeRuntime(QuickEntrypointEnum entrypoint,
1065 HInstruction* instruction,
1066 uint32_t dex_pc,
1067 SlowPathCode* slow_path) {
1068 InvokeRuntime(GetThreadOffset<kMipsWordSize>(entrypoint).Int32Value(),
1069 instruction,
1070 dex_pc,
1071 slow_path,
1072 IsDirectEntrypoint(entrypoint));
1073 }
1074
1075 constexpr size_t kMipsDirectEntrypointRuntimeOffset = 16;
1076
InvokeRuntime(int32_t entry_point_offset,HInstruction * instruction,uint32_t dex_pc,SlowPathCode * slow_path,bool is_direct_entrypoint)1077 void CodeGeneratorMIPS::InvokeRuntime(int32_t entry_point_offset,
1078 HInstruction* instruction,
1079 uint32_t dex_pc,
1080 SlowPathCode* slow_path,
1081 bool is_direct_entrypoint) {
1082 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset);
1083 __ Jalr(T9);
1084 if (is_direct_entrypoint) {
1085 // Reserve argument space on stack (for $a0-$a3) for
1086 // entrypoints that directly reference native implementations.
1087 // Called function may use this space to store $a0-$a3 regs.
1088 __ IncreaseFrameSize(kMipsDirectEntrypointRuntimeOffset); // Single instruction in delay slot.
1089 __ DecreaseFrameSize(kMipsDirectEntrypointRuntimeOffset);
1090 } else {
1091 __ Nop(); // In delay slot.
1092 }
1093 RecordPcInfo(instruction, dex_pc, slow_path);
1094 }
1095
GenerateClassInitializationCheck(SlowPathCodeMIPS * slow_path,Register class_reg)1096 void InstructionCodeGeneratorMIPS::GenerateClassInitializationCheck(SlowPathCodeMIPS* slow_path,
1097 Register class_reg) {
1098 __ LoadFromOffset(kLoadWord, TMP, class_reg, mirror::Class::StatusOffset().Int32Value());
1099 __ LoadConst32(AT, mirror::Class::kStatusInitialized);
1100 __ Blt(TMP, AT, slow_path->GetEntryLabel());
1101 // Even if the initialized flag is set, we need to ensure consistent memory ordering.
1102 __ Sync(0);
1103 __ Bind(slow_path->GetExitLabel());
1104 }
1105
GenerateMemoryBarrier(MemBarrierKind kind ATTRIBUTE_UNUSED)1106 void InstructionCodeGeneratorMIPS::GenerateMemoryBarrier(MemBarrierKind kind ATTRIBUTE_UNUSED) {
1107 __ Sync(0); // Only stype 0 is supported.
1108 }
1109
GenerateSuspendCheck(HSuspendCheck * instruction,HBasicBlock * successor)1110 void InstructionCodeGeneratorMIPS::GenerateSuspendCheck(HSuspendCheck* instruction,
1111 HBasicBlock* successor) {
1112 SuspendCheckSlowPathMIPS* slow_path =
1113 new (GetGraph()->GetArena()) SuspendCheckSlowPathMIPS(instruction, successor);
1114 codegen_->AddSlowPath(slow_path);
1115
1116 __ LoadFromOffset(kLoadUnsignedHalfword,
1117 TMP,
1118 TR,
1119 Thread::ThreadFlagsOffset<kMipsWordSize>().Int32Value());
1120 if (successor == nullptr) {
1121 __ Bnez(TMP, slow_path->GetEntryLabel());
1122 __ Bind(slow_path->GetReturnLabel());
1123 } else {
1124 __ Beqz(TMP, codegen_->GetLabelOf(successor));
1125 __ B(slow_path->GetEntryLabel());
1126 // slow_path will return to GetLabelOf(successor).
1127 }
1128 }
1129
InstructionCodeGeneratorMIPS(HGraph * graph,CodeGeneratorMIPS * codegen)1130 InstructionCodeGeneratorMIPS::InstructionCodeGeneratorMIPS(HGraph* graph,
1131 CodeGeneratorMIPS* codegen)
1132 : InstructionCodeGenerator(graph, codegen),
1133 assembler_(codegen->GetAssembler()),
1134 codegen_(codegen) {}
1135
HandleBinaryOp(HBinaryOperation * instruction)1136 void LocationsBuilderMIPS::HandleBinaryOp(HBinaryOperation* instruction) {
1137 DCHECK_EQ(instruction->InputCount(), 2U);
1138 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
1139 Primitive::Type type = instruction->GetResultType();
1140 switch (type) {
1141 case Primitive::kPrimInt: {
1142 locations->SetInAt(0, Location::RequiresRegister());
1143 HInstruction* right = instruction->InputAt(1);
1144 bool can_use_imm = false;
1145 if (right->IsConstant()) {
1146 int32_t imm = CodeGenerator::GetInt32ValueOf(right->AsConstant());
1147 if (instruction->IsAnd() || instruction->IsOr() || instruction->IsXor()) {
1148 can_use_imm = IsUint<16>(imm);
1149 } else if (instruction->IsAdd()) {
1150 can_use_imm = IsInt<16>(imm);
1151 } else {
1152 DCHECK(instruction->IsSub());
1153 can_use_imm = IsInt<16>(-imm);
1154 }
1155 }
1156 if (can_use_imm)
1157 locations->SetInAt(1, Location::ConstantLocation(right->AsConstant()));
1158 else
1159 locations->SetInAt(1, Location::RequiresRegister());
1160 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1161 break;
1162 }
1163
1164 case Primitive::kPrimLong: {
1165 locations->SetInAt(0, Location::RequiresRegister());
1166 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
1167 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1168 break;
1169 }
1170
1171 case Primitive::kPrimFloat:
1172 case Primitive::kPrimDouble:
1173 DCHECK(instruction->IsAdd() || instruction->IsSub());
1174 locations->SetInAt(0, Location::RequiresFpuRegister());
1175 locations->SetInAt(1, Location::RequiresFpuRegister());
1176 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
1177 break;
1178
1179 default:
1180 LOG(FATAL) << "Unexpected " << instruction->DebugName() << " type " << type;
1181 }
1182 }
1183
HandleBinaryOp(HBinaryOperation * instruction)1184 void InstructionCodeGeneratorMIPS::HandleBinaryOp(HBinaryOperation* instruction) {
1185 Primitive::Type type = instruction->GetType();
1186 LocationSummary* locations = instruction->GetLocations();
1187
1188 switch (type) {
1189 case Primitive::kPrimInt: {
1190 Register dst = locations->Out().AsRegister<Register>();
1191 Register lhs = locations->InAt(0).AsRegister<Register>();
1192 Location rhs_location = locations->InAt(1);
1193
1194 Register rhs_reg = ZERO;
1195 int32_t rhs_imm = 0;
1196 bool use_imm = rhs_location.IsConstant();
1197 if (use_imm) {
1198 rhs_imm = CodeGenerator::GetInt32ValueOf(rhs_location.GetConstant());
1199 } else {
1200 rhs_reg = rhs_location.AsRegister<Register>();
1201 }
1202
1203 if (instruction->IsAnd()) {
1204 if (use_imm)
1205 __ Andi(dst, lhs, rhs_imm);
1206 else
1207 __ And(dst, lhs, rhs_reg);
1208 } else if (instruction->IsOr()) {
1209 if (use_imm)
1210 __ Ori(dst, lhs, rhs_imm);
1211 else
1212 __ Or(dst, lhs, rhs_reg);
1213 } else if (instruction->IsXor()) {
1214 if (use_imm)
1215 __ Xori(dst, lhs, rhs_imm);
1216 else
1217 __ Xor(dst, lhs, rhs_reg);
1218 } else if (instruction->IsAdd()) {
1219 if (use_imm)
1220 __ Addiu(dst, lhs, rhs_imm);
1221 else
1222 __ Addu(dst, lhs, rhs_reg);
1223 } else {
1224 DCHECK(instruction->IsSub());
1225 if (use_imm)
1226 __ Addiu(dst, lhs, -rhs_imm);
1227 else
1228 __ Subu(dst, lhs, rhs_reg);
1229 }
1230 break;
1231 }
1232
1233 case Primitive::kPrimLong: {
1234 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1235 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
1236 Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
1237 Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
1238 Location rhs_location = locations->InAt(1);
1239 bool use_imm = rhs_location.IsConstant();
1240 if (!use_imm) {
1241 Register rhs_high = rhs_location.AsRegisterPairHigh<Register>();
1242 Register rhs_low = rhs_location.AsRegisterPairLow<Register>();
1243 if (instruction->IsAnd()) {
1244 __ And(dst_low, lhs_low, rhs_low);
1245 __ And(dst_high, lhs_high, rhs_high);
1246 } else if (instruction->IsOr()) {
1247 __ Or(dst_low, lhs_low, rhs_low);
1248 __ Or(dst_high, lhs_high, rhs_high);
1249 } else if (instruction->IsXor()) {
1250 __ Xor(dst_low, lhs_low, rhs_low);
1251 __ Xor(dst_high, lhs_high, rhs_high);
1252 } else if (instruction->IsAdd()) {
1253 if (lhs_low == rhs_low) {
1254 // Special case for lhs = rhs and the sum potentially overwriting both lhs and rhs.
1255 __ Slt(TMP, lhs_low, ZERO);
1256 __ Addu(dst_low, lhs_low, rhs_low);
1257 } else {
1258 __ Addu(dst_low, lhs_low, rhs_low);
1259 // If the sum overwrites rhs, lhs remains unchanged, otherwise rhs remains unchanged.
1260 __ Sltu(TMP, dst_low, (dst_low == rhs_low) ? lhs_low : rhs_low);
1261 }
1262 __ Addu(dst_high, lhs_high, rhs_high);
1263 __ Addu(dst_high, dst_high, TMP);
1264 } else {
1265 DCHECK(instruction->IsSub());
1266 __ Sltu(TMP, lhs_low, rhs_low);
1267 __ Subu(dst_low, lhs_low, rhs_low);
1268 __ Subu(dst_high, lhs_high, rhs_high);
1269 __ Subu(dst_high, dst_high, TMP);
1270 }
1271 } else {
1272 int64_t value = CodeGenerator::GetInt64ValueOf(rhs_location.GetConstant()->AsConstant());
1273 if (instruction->IsOr()) {
1274 uint32_t low = Low32Bits(value);
1275 uint32_t high = High32Bits(value);
1276 if (IsUint<16>(low)) {
1277 if (dst_low != lhs_low || low != 0) {
1278 __ Ori(dst_low, lhs_low, low);
1279 }
1280 } else {
1281 __ LoadConst32(TMP, low);
1282 __ Or(dst_low, lhs_low, TMP);
1283 }
1284 if (IsUint<16>(high)) {
1285 if (dst_high != lhs_high || high != 0) {
1286 __ Ori(dst_high, lhs_high, high);
1287 }
1288 } else {
1289 if (high != low) {
1290 __ LoadConst32(TMP, high);
1291 }
1292 __ Or(dst_high, lhs_high, TMP);
1293 }
1294 } else if (instruction->IsXor()) {
1295 uint32_t low = Low32Bits(value);
1296 uint32_t high = High32Bits(value);
1297 if (IsUint<16>(low)) {
1298 if (dst_low != lhs_low || low != 0) {
1299 __ Xori(dst_low, lhs_low, low);
1300 }
1301 } else {
1302 __ LoadConst32(TMP, low);
1303 __ Xor(dst_low, lhs_low, TMP);
1304 }
1305 if (IsUint<16>(high)) {
1306 if (dst_high != lhs_high || high != 0) {
1307 __ Xori(dst_high, lhs_high, high);
1308 }
1309 } else {
1310 if (high != low) {
1311 __ LoadConst32(TMP, high);
1312 }
1313 __ Xor(dst_high, lhs_high, TMP);
1314 }
1315 } else if (instruction->IsAnd()) {
1316 uint32_t low = Low32Bits(value);
1317 uint32_t high = High32Bits(value);
1318 if (IsUint<16>(low)) {
1319 __ Andi(dst_low, lhs_low, low);
1320 } else if (low != 0xFFFFFFFF) {
1321 __ LoadConst32(TMP, low);
1322 __ And(dst_low, lhs_low, TMP);
1323 } else if (dst_low != lhs_low) {
1324 __ Move(dst_low, lhs_low);
1325 }
1326 if (IsUint<16>(high)) {
1327 __ Andi(dst_high, lhs_high, high);
1328 } else if (high != 0xFFFFFFFF) {
1329 if (high != low) {
1330 __ LoadConst32(TMP, high);
1331 }
1332 __ And(dst_high, lhs_high, TMP);
1333 } else if (dst_high != lhs_high) {
1334 __ Move(dst_high, lhs_high);
1335 }
1336 } else {
1337 if (instruction->IsSub()) {
1338 value = -value;
1339 } else {
1340 DCHECK(instruction->IsAdd());
1341 }
1342 int32_t low = Low32Bits(value);
1343 int32_t high = High32Bits(value);
1344 if (IsInt<16>(low)) {
1345 if (dst_low != lhs_low || low != 0) {
1346 __ Addiu(dst_low, lhs_low, low);
1347 }
1348 if (low != 0) {
1349 __ Sltiu(AT, dst_low, low);
1350 }
1351 } else {
1352 __ LoadConst32(TMP, low);
1353 __ Addu(dst_low, lhs_low, TMP);
1354 __ Sltu(AT, dst_low, TMP);
1355 }
1356 if (IsInt<16>(high)) {
1357 if (dst_high != lhs_high || high != 0) {
1358 __ Addiu(dst_high, lhs_high, high);
1359 }
1360 } else {
1361 if (high != low) {
1362 __ LoadConst32(TMP, high);
1363 }
1364 __ Addu(dst_high, lhs_high, TMP);
1365 }
1366 if (low != 0) {
1367 __ Addu(dst_high, dst_high, AT);
1368 }
1369 }
1370 }
1371 break;
1372 }
1373
1374 case Primitive::kPrimFloat:
1375 case Primitive::kPrimDouble: {
1376 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
1377 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
1378 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
1379 if (instruction->IsAdd()) {
1380 if (type == Primitive::kPrimFloat) {
1381 __ AddS(dst, lhs, rhs);
1382 } else {
1383 __ AddD(dst, lhs, rhs);
1384 }
1385 } else {
1386 DCHECK(instruction->IsSub());
1387 if (type == Primitive::kPrimFloat) {
1388 __ SubS(dst, lhs, rhs);
1389 } else {
1390 __ SubD(dst, lhs, rhs);
1391 }
1392 }
1393 break;
1394 }
1395
1396 default:
1397 LOG(FATAL) << "Unexpected binary operation type " << type;
1398 }
1399 }
1400
HandleShift(HBinaryOperation * instr)1401 void LocationsBuilderMIPS::HandleShift(HBinaryOperation* instr) {
1402 DCHECK(instr->IsShl() || instr->IsShr() || instr->IsUShr() || instr->IsRor());
1403
1404 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instr);
1405 Primitive::Type type = instr->GetResultType();
1406 switch (type) {
1407 case Primitive::kPrimInt:
1408 locations->SetInAt(0, Location::RequiresRegister());
1409 locations->SetInAt(1, Location::RegisterOrConstant(instr->InputAt(1)));
1410 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1411 break;
1412 case Primitive::kPrimLong:
1413 locations->SetInAt(0, Location::RequiresRegister());
1414 locations->SetInAt(1, Location::RegisterOrConstant(instr->InputAt(1)));
1415 locations->SetOut(Location::RequiresRegister());
1416 break;
1417 default:
1418 LOG(FATAL) << "Unexpected shift type " << type;
1419 }
1420 }
1421
1422 static constexpr size_t kMipsBitsPerWord = kMipsWordSize * kBitsPerByte;
1423
HandleShift(HBinaryOperation * instr)1424 void InstructionCodeGeneratorMIPS::HandleShift(HBinaryOperation* instr) {
1425 DCHECK(instr->IsShl() || instr->IsShr() || instr->IsUShr() || instr->IsRor());
1426 LocationSummary* locations = instr->GetLocations();
1427 Primitive::Type type = instr->GetType();
1428
1429 Location rhs_location = locations->InAt(1);
1430 bool use_imm = rhs_location.IsConstant();
1431 Register rhs_reg = use_imm ? ZERO : rhs_location.AsRegister<Register>();
1432 int64_t rhs_imm = use_imm ? CodeGenerator::GetInt64ValueOf(rhs_location.GetConstant()) : 0;
1433 const uint32_t shift_mask =
1434 (type == Primitive::kPrimInt) ? kMaxIntShiftDistance : kMaxLongShiftDistance;
1435 const uint32_t shift_value = rhs_imm & shift_mask;
1436 // Are the INS (Insert Bit Field) and ROTR instructions supported?
1437 bool has_ins_rotr = codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2();
1438
1439 switch (type) {
1440 case Primitive::kPrimInt: {
1441 Register dst = locations->Out().AsRegister<Register>();
1442 Register lhs = locations->InAt(0).AsRegister<Register>();
1443 if (use_imm) {
1444 if (shift_value == 0) {
1445 if (dst != lhs) {
1446 __ Move(dst, lhs);
1447 }
1448 } else if (instr->IsShl()) {
1449 __ Sll(dst, lhs, shift_value);
1450 } else if (instr->IsShr()) {
1451 __ Sra(dst, lhs, shift_value);
1452 } else if (instr->IsUShr()) {
1453 __ Srl(dst, lhs, shift_value);
1454 } else {
1455 if (has_ins_rotr) {
1456 __ Rotr(dst, lhs, shift_value);
1457 } else {
1458 __ Sll(TMP, lhs, (kMipsBitsPerWord - shift_value) & shift_mask);
1459 __ Srl(dst, lhs, shift_value);
1460 __ Or(dst, dst, TMP);
1461 }
1462 }
1463 } else {
1464 if (instr->IsShl()) {
1465 __ Sllv(dst, lhs, rhs_reg);
1466 } else if (instr->IsShr()) {
1467 __ Srav(dst, lhs, rhs_reg);
1468 } else if (instr->IsUShr()) {
1469 __ Srlv(dst, lhs, rhs_reg);
1470 } else {
1471 if (has_ins_rotr) {
1472 __ Rotrv(dst, lhs, rhs_reg);
1473 } else {
1474 __ Subu(TMP, ZERO, rhs_reg);
1475 // 32-bit shift instructions use the 5 least significant bits of the shift count, so
1476 // shifting by `-rhs_reg` is equivalent to shifting by `(32 - rhs_reg) & 31`. The case
1477 // when `rhs_reg & 31 == 0` is OK even though we don't shift `lhs` left all the way out
1478 // by 32, because the result in this case is computed as `(lhs >> 0) | (lhs << 0)`,
1479 // IOW, the OR'd values are equal.
1480 __ Sllv(TMP, lhs, TMP);
1481 __ Srlv(dst, lhs, rhs_reg);
1482 __ Or(dst, dst, TMP);
1483 }
1484 }
1485 }
1486 break;
1487 }
1488
1489 case Primitive::kPrimLong: {
1490 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1491 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
1492 Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
1493 Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
1494 if (use_imm) {
1495 if (shift_value == 0) {
1496 codegen_->Move64(locations->Out(), locations->InAt(0));
1497 } else if (shift_value < kMipsBitsPerWord) {
1498 if (has_ins_rotr) {
1499 if (instr->IsShl()) {
1500 __ Srl(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
1501 __ Ins(dst_high, lhs_high, shift_value, kMipsBitsPerWord - shift_value);
1502 __ Sll(dst_low, lhs_low, shift_value);
1503 } else if (instr->IsShr()) {
1504 __ Srl(dst_low, lhs_low, shift_value);
1505 __ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
1506 __ Sra(dst_high, lhs_high, shift_value);
1507 } else if (instr->IsUShr()) {
1508 __ Srl(dst_low, lhs_low, shift_value);
1509 __ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
1510 __ Srl(dst_high, lhs_high, shift_value);
1511 } else {
1512 __ Srl(dst_low, lhs_low, shift_value);
1513 __ Ins(dst_low, lhs_high, kMipsBitsPerWord - shift_value, shift_value);
1514 __ Srl(dst_high, lhs_high, shift_value);
1515 __ Ins(dst_high, lhs_low, kMipsBitsPerWord - shift_value, shift_value);
1516 }
1517 } else {
1518 if (instr->IsShl()) {
1519 __ Sll(dst_low, lhs_low, shift_value);
1520 __ Srl(TMP, lhs_low, kMipsBitsPerWord - shift_value);
1521 __ Sll(dst_high, lhs_high, shift_value);
1522 __ Or(dst_high, dst_high, TMP);
1523 } else if (instr->IsShr()) {
1524 __ Sra(dst_high, lhs_high, shift_value);
1525 __ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value);
1526 __ Srl(dst_low, lhs_low, shift_value);
1527 __ Or(dst_low, dst_low, TMP);
1528 } else if (instr->IsUShr()) {
1529 __ Srl(dst_high, lhs_high, shift_value);
1530 __ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value);
1531 __ Srl(dst_low, lhs_low, shift_value);
1532 __ Or(dst_low, dst_low, TMP);
1533 } else {
1534 __ Srl(TMP, lhs_low, shift_value);
1535 __ Sll(dst_low, lhs_high, kMipsBitsPerWord - shift_value);
1536 __ Or(dst_low, dst_low, TMP);
1537 __ Srl(TMP, lhs_high, shift_value);
1538 __ Sll(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
1539 __ Or(dst_high, dst_high, TMP);
1540 }
1541 }
1542 } else {
1543 const uint32_t shift_value_high = shift_value - kMipsBitsPerWord;
1544 if (instr->IsShl()) {
1545 __ Sll(dst_high, lhs_low, shift_value_high);
1546 __ Move(dst_low, ZERO);
1547 } else if (instr->IsShr()) {
1548 __ Sra(dst_low, lhs_high, shift_value_high);
1549 __ Sra(dst_high, dst_low, kMipsBitsPerWord - 1);
1550 } else if (instr->IsUShr()) {
1551 __ Srl(dst_low, lhs_high, shift_value_high);
1552 __ Move(dst_high, ZERO);
1553 } else {
1554 if (shift_value == kMipsBitsPerWord) {
1555 // 64-bit rotation by 32 is just a swap.
1556 __ Move(dst_low, lhs_high);
1557 __ Move(dst_high, lhs_low);
1558 } else {
1559 if (has_ins_rotr) {
1560 __ Srl(dst_low, lhs_high, shift_value_high);
1561 __ Ins(dst_low, lhs_low, kMipsBitsPerWord - shift_value_high, shift_value_high);
1562 __ Srl(dst_high, lhs_low, shift_value_high);
1563 __ Ins(dst_high, lhs_high, kMipsBitsPerWord - shift_value_high, shift_value_high);
1564 } else {
1565 __ Sll(TMP, lhs_low, kMipsBitsPerWord - shift_value_high);
1566 __ Srl(dst_low, lhs_high, shift_value_high);
1567 __ Or(dst_low, dst_low, TMP);
1568 __ Sll(TMP, lhs_high, kMipsBitsPerWord - shift_value_high);
1569 __ Srl(dst_high, lhs_low, shift_value_high);
1570 __ Or(dst_high, dst_high, TMP);
1571 }
1572 }
1573 }
1574 }
1575 } else {
1576 MipsLabel done;
1577 if (instr->IsShl()) {
1578 __ Sllv(dst_low, lhs_low, rhs_reg);
1579 __ Nor(AT, ZERO, rhs_reg);
1580 __ Srl(TMP, lhs_low, 1);
1581 __ Srlv(TMP, TMP, AT);
1582 __ Sllv(dst_high, lhs_high, rhs_reg);
1583 __ Or(dst_high, dst_high, TMP);
1584 __ Andi(TMP, rhs_reg, kMipsBitsPerWord);
1585 __ Beqz(TMP, &done);
1586 __ Move(dst_high, dst_low);
1587 __ Move(dst_low, ZERO);
1588 } else if (instr->IsShr()) {
1589 __ Srav(dst_high, lhs_high, rhs_reg);
1590 __ Nor(AT, ZERO, rhs_reg);
1591 __ Sll(TMP, lhs_high, 1);
1592 __ Sllv(TMP, TMP, AT);
1593 __ Srlv(dst_low, lhs_low, rhs_reg);
1594 __ Or(dst_low, dst_low, TMP);
1595 __ Andi(TMP, rhs_reg, kMipsBitsPerWord);
1596 __ Beqz(TMP, &done);
1597 __ Move(dst_low, dst_high);
1598 __ Sra(dst_high, dst_high, 31);
1599 } else if (instr->IsUShr()) {
1600 __ Srlv(dst_high, lhs_high, rhs_reg);
1601 __ Nor(AT, ZERO, rhs_reg);
1602 __ Sll(TMP, lhs_high, 1);
1603 __ Sllv(TMP, TMP, AT);
1604 __ Srlv(dst_low, lhs_low, rhs_reg);
1605 __ Or(dst_low, dst_low, TMP);
1606 __ Andi(TMP, rhs_reg, kMipsBitsPerWord);
1607 __ Beqz(TMP, &done);
1608 __ Move(dst_low, dst_high);
1609 __ Move(dst_high, ZERO);
1610 } else {
1611 __ Nor(AT, ZERO, rhs_reg);
1612 __ Srlv(TMP, lhs_low, rhs_reg);
1613 __ Sll(dst_low, lhs_high, 1);
1614 __ Sllv(dst_low, dst_low, AT);
1615 __ Or(dst_low, dst_low, TMP);
1616 __ Srlv(TMP, lhs_high, rhs_reg);
1617 __ Sll(dst_high, lhs_low, 1);
1618 __ Sllv(dst_high, dst_high, AT);
1619 __ Or(dst_high, dst_high, TMP);
1620 __ Andi(TMP, rhs_reg, kMipsBitsPerWord);
1621 __ Beqz(TMP, &done);
1622 __ Move(TMP, dst_high);
1623 __ Move(dst_high, dst_low);
1624 __ Move(dst_low, TMP);
1625 }
1626 __ Bind(&done);
1627 }
1628 break;
1629 }
1630
1631 default:
1632 LOG(FATAL) << "Unexpected shift operation type " << type;
1633 }
1634 }
1635
VisitAdd(HAdd * instruction)1636 void LocationsBuilderMIPS::VisitAdd(HAdd* instruction) {
1637 HandleBinaryOp(instruction);
1638 }
1639
VisitAdd(HAdd * instruction)1640 void InstructionCodeGeneratorMIPS::VisitAdd(HAdd* instruction) {
1641 HandleBinaryOp(instruction);
1642 }
1643
VisitAnd(HAnd * instruction)1644 void LocationsBuilderMIPS::VisitAnd(HAnd* instruction) {
1645 HandleBinaryOp(instruction);
1646 }
1647
VisitAnd(HAnd * instruction)1648 void InstructionCodeGeneratorMIPS::VisitAnd(HAnd* instruction) {
1649 HandleBinaryOp(instruction);
1650 }
1651
VisitArrayGet(HArrayGet * instruction)1652 void LocationsBuilderMIPS::VisitArrayGet(HArrayGet* instruction) {
1653 LocationSummary* locations =
1654 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall);
1655 locations->SetInAt(0, Location::RequiresRegister());
1656 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
1657 if (Primitive::IsFloatingPointType(instruction->GetType())) {
1658 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
1659 } else {
1660 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1661 }
1662 }
1663
VisitArrayGet(HArrayGet * instruction)1664 void InstructionCodeGeneratorMIPS::VisitArrayGet(HArrayGet* instruction) {
1665 LocationSummary* locations = instruction->GetLocations();
1666 Register obj = locations->InAt(0).AsRegister<Register>();
1667 Location index = locations->InAt(1);
1668 Primitive::Type type = instruction->GetType();
1669
1670 switch (type) {
1671 case Primitive::kPrimBoolean: {
1672 uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint8_t)).Uint32Value();
1673 Register out = locations->Out().AsRegister<Register>();
1674 if (index.IsConstant()) {
1675 size_t offset =
1676 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
1677 __ LoadFromOffset(kLoadUnsignedByte, out, obj, offset);
1678 } else {
1679 __ Addu(TMP, obj, index.AsRegister<Register>());
1680 __ LoadFromOffset(kLoadUnsignedByte, out, TMP, data_offset);
1681 }
1682 break;
1683 }
1684
1685 case Primitive::kPrimByte: {
1686 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int8_t)).Uint32Value();
1687 Register out = locations->Out().AsRegister<Register>();
1688 if (index.IsConstant()) {
1689 size_t offset =
1690 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
1691 __ LoadFromOffset(kLoadSignedByte, out, obj, offset);
1692 } else {
1693 __ Addu(TMP, obj, index.AsRegister<Register>());
1694 __ LoadFromOffset(kLoadSignedByte, out, TMP, data_offset);
1695 }
1696 break;
1697 }
1698
1699 case Primitive::kPrimShort: {
1700 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int16_t)).Uint32Value();
1701 Register out = locations->Out().AsRegister<Register>();
1702 if (index.IsConstant()) {
1703 size_t offset =
1704 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
1705 __ LoadFromOffset(kLoadSignedHalfword, out, obj, offset);
1706 } else {
1707 __ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
1708 __ Addu(TMP, obj, TMP);
1709 __ LoadFromOffset(kLoadSignedHalfword, out, TMP, data_offset);
1710 }
1711 break;
1712 }
1713
1714 case Primitive::kPrimChar: {
1715 uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Uint32Value();
1716 Register out = locations->Out().AsRegister<Register>();
1717 if (index.IsConstant()) {
1718 size_t offset =
1719 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
1720 __ LoadFromOffset(kLoadUnsignedHalfword, out, obj, offset);
1721 } else {
1722 __ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
1723 __ Addu(TMP, obj, TMP);
1724 __ LoadFromOffset(kLoadUnsignedHalfword, out, TMP, data_offset);
1725 }
1726 break;
1727 }
1728
1729 case Primitive::kPrimInt:
1730 case Primitive::kPrimNot: {
1731 DCHECK_EQ(sizeof(mirror::HeapReference<mirror::Object>), sizeof(int32_t));
1732 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Uint32Value();
1733 Register out = locations->Out().AsRegister<Register>();
1734 if (index.IsConstant()) {
1735 size_t offset =
1736 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
1737 __ LoadFromOffset(kLoadWord, out, obj, offset);
1738 } else {
1739 __ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
1740 __ Addu(TMP, obj, TMP);
1741 __ LoadFromOffset(kLoadWord, out, TMP, data_offset);
1742 }
1743 break;
1744 }
1745
1746 case Primitive::kPrimLong: {
1747 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Uint32Value();
1748 Register out = locations->Out().AsRegisterPairLow<Register>();
1749 if (index.IsConstant()) {
1750 size_t offset =
1751 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1752 __ LoadFromOffset(kLoadDoubleword, out, obj, offset);
1753 } else {
1754 __ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
1755 __ Addu(TMP, obj, TMP);
1756 __ LoadFromOffset(kLoadDoubleword, out, TMP, data_offset);
1757 }
1758 break;
1759 }
1760
1761 case Primitive::kPrimFloat: {
1762 uint32_t data_offset = mirror::Array::DataOffset(sizeof(float)).Uint32Value();
1763 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1764 if (index.IsConstant()) {
1765 size_t offset =
1766 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
1767 __ LoadSFromOffset(out, obj, offset);
1768 } else {
1769 __ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
1770 __ Addu(TMP, obj, TMP);
1771 __ LoadSFromOffset(out, TMP, data_offset);
1772 }
1773 break;
1774 }
1775
1776 case Primitive::kPrimDouble: {
1777 uint32_t data_offset = mirror::Array::DataOffset(sizeof(double)).Uint32Value();
1778 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1779 if (index.IsConstant()) {
1780 size_t offset =
1781 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1782 __ LoadDFromOffset(out, obj, offset);
1783 } else {
1784 __ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
1785 __ Addu(TMP, obj, TMP);
1786 __ LoadDFromOffset(out, TMP, data_offset);
1787 }
1788 break;
1789 }
1790
1791 case Primitive::kPrimVoid:
1792 LOG(FATAL) << "Unreachable type " << instruction->GetType();
1793 UNREACHABLE();
1794 }
1795 codegen_->MaybeRecordImplicitNullCheck(instruction);
1796 }
1797
VisitArrayLength(HArrayLength * instruction)1798 void LocationsBuilderMIPS::VisitArrayLength(HArrayLength* instruction) {
1799 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
1800 locations->SetInAt(0, Location::RequiresRegister());
1801 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
1802 }
1803
VisitArrayLength(HArrayLength * instruction)1804 void InstructionCodeGeneratorMIPS::VisitArrayLength(HArrayLength* instruction) {
1805 LocationSummary* locations = instruction->GetLocations();
1806 uint32_t offset = mirror::Array::LengthOffset().Uint32Value();
1807 Register obj = locations->InAt(0).AsRegister<Register>();
1808 Register out = locations->Out().AsRegister<Register>();
1809 __ LoadFromOffset(kLoadWord, out, obj, offset);
1810 codegen_->MaybeRecordImplicitNullCheck(instruction);
1811 }
1812
VisitArraySet(HArraySet * instruction)1813 void LocationsBuilderMIPS::VisitArraySet(HArraySet* instruction) {
1814 bool needs_runtime_call = instruction->NeedsTypeCheck();
1815 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
1816 instruction,
1817 needs_runtime_call ? LocationSummary::kCall : LocationSummary::kNoCall);
1818 if (needs_runtime_call) {
1819 InvokeRuntimeCallingConvention calling_convention;
1820 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
1821 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1)));
1822 locations->SetInAt(2, Location::RegisterLocation(calling_convention.GetRegisterAt(2)));
1823 } else {
1824 locations->SetInAt(0, Location::RequiresRegister());
1825 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
1826 if (Primitive::IsFloatingPointType(instruction->InputAt(2)->GetType())) {
1827 locations->SetInAt(2, Location::RequiresFpuRegister());
1828 } else {
1829 locations->SetInAt(2, Location::RequiresRegister());
1830 }
1831 }
1832 }
1833
VisitArraySet(HArraySet * instruction)1834 void InstructionCodeGeneratorMIPS::VisitArraySet(HArraySet* instruction) {
1835 LocationSummary* locations = instruction->GetLocations();
1836 Register obj = locations->InAt(0).AsRegister<Register>();
1837 Location index = locations->InAt(1);
1838 Primitive::Type value_type = instruction->GetComponentType();
1839 bool needs_runtime_call = locations->WillCall();
1840 bool needs_write_barrier =
1841 CodeGenerator::StoreNeedsWriteBarrier(value_type, instruction->GetValue());
1842
1843 switch (value_type) {
1844 case Primitive::kPrimBoolean:
1845 case Primitive::kPrimByte: {
1846 uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint8_t)).Uint32Value();
1847 Register value = locations->InAt(2).AsRegister<Register>();
1848 if (index.IsConstant()) {
1849 size_t offset =
1850 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_1) + data_offset;
1851 __ StoreToOffset(kStoreByte, value, obj, offset);
1852 } else {
1853 __ Addu(TMP, obj, index.AsRegister<Register>());
1854 __ StoreToOffset(kStoreByte, value, TMP, data_offset);
1855 }
1856 break;
1857 }
1858
1859 case Primitive::kPrimShort:
1860 case Primitive::kPrimChar: {
1861 uint32_t data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Uint32Value();
1862 Register value = locations->InAt(2).AsRegister<Register>();
1863 if (index.IsConstant()) {
1864 size_t offset =
1865 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_2) + data_offset;
1866 __ StoreToOffset(kStoreHalfword, value, obj, offset);
1867 } else {
1868 __ Sll(TMP, index.AsRegister<Register>(), TIMES_2);
1869 __ Addu(TMP, obj, TMP);
1870 __ StoreToOffset(kStoreHalfword, value, TMP, data_offset);
1871 }
1872 break;
1873 }
1874
1875 case Primitive::kPrimInt:
1876 case Primitive::kPrimNot: {
1877 if (!needs_runtime_call) {
1878 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int32_t)).Uint32Value();
1879 Register value = locations->InAt(2).AsRegister<Register>();
1880 if (index.IsConstant()) {
1881 size_t offset =
1882 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
1883 __ StoreToOffset(kStoreWord, value, obj, offset);
1884 } else {
1885 DCHECK(index.IsRegister()) << index;
1886 __ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
1887 __ Addu(TMP, obj, TMP);
1888 __ StoreToOffset(kStoreWord, value, TMP, data_offset);
1889 }
1890 codegen_->MaybeRecordImplicitNullCheck(instruction);
1891 if (needs_write_barrier) {
1892 DCHECK_EQ(value_type, Primitive::kPrimNot);
1893 codegen_->MarkGCCard(obj, value);
1894 }
1895 } else {
1896 DCHECK_EQ(value_type, Primitive::kPrimNot);
1897 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pAputObject),
1898 instruction,
1899 instruction->GetDexPc(),
1900 nullptr,
1901 IsDirectEntrypoint(kQuickAputObject));
1902 CheckEntrypointTypes<kQuickAputObject, void, mirror::Array*, int32_t, mirror::Object*>();
1903 }
1904 break;
1905 }
1906
1907 case Primitive::kPrimLong: {
1908 uint32_t data_offset = mirror::Array::DataOffset(sizeof(int64_t)).Uint32Value();
1909 Register value = locations->InAt(2).AsRegisterPairLow<Register>();
1910 if (index.IsConstant()) {
1911 size_t offset =
1912 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1913 __ StoreToOffset(kStoreDoubleword, value, obj, offset);
1914 } else {
1915 __ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
1916 __ Addu(TMP, obj, TMP);
1917 __ StoreToOffset(kStoreDoubleword, value, TMP, data_offset);
1918 }
1919 break;
1920 }
1921
1922 case Primitive::kPrimFloat: {
1923 uint32_t data_offset = mirror::Array::DataOffset(sizeof(float)).Uint32Value();
1924 FRegister value = locations->InAt(2).AsFpuRegister<FRegister>();
1925 DCHECK(locations->InAt(2).IsFpuRegister());
1926 if (index.IsConstant()) {
1927 size_t offset =
1928 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_4) + data_offset;
1929 __ StoreSToOffset(value, obj, offset);
1930 } else {
1931 __ Sll(TMP, index.AsRegister<Register>(), TIMES_4);
1932 __ Addu(TMP, obj, TMP);
1933 __ StoreSToOffset(value, TMP, data_offset);
1934 }
1935 break;
1936 }
1937
1938 case Primitive::kPrimDouble: {
1939 uint32_t data_offset = mirror::Array::DataOffset(sizeof(double)).Uint32Value();
1940 FRegister value = locations->InAt(2).AsFpuRegister<FRegister>();
1941 DCHECK(locations->InAt(2).IsFpuRegister());
1942 if (index.IsConstant()) {
1943 size_t offset =
1944 (index.GetConstant()->AsIntConstant()->GetValue() << TIMES_8) + data_offset;
1945 __ StoreDToOffset(value, obj, offset);
1946 } else {
1947 __ Sll(TMP, index.AsRegister<Register>(), TIMES_8);
1948 __ Addu(TMP, obj, TMP);
1949 __ StoreDToOffset(value, TMP, data_offset);
1950 }
1951 break;
1952 }
1953
1954 case Primitive::kPrimVoid:
1955 LOG(FATAL) << "Unreachable type " << instruction->GetType();
1956 UNREACHABLE();
1957 }
1958
1959 // Ints and objects are handled in the switch.
1960 if (value_type != Primitive::kPrimInt && value_type != Primitive::kPrimNot) {
1961 codegen_->MaybeRecordImplicitNullCheck(instruction);
1962 }
1963 }
1964
VisitBoundsCheck(HBoundsCheck * instruction)1965 void LocationsBuilderMIPS::VisitBoundsCheck(HBoundsCheck* instruction) {
1966 LocationSummary::CallKind call_kind = instruction->CanThrowIntoCatchBlock()
1967 ? LocationSummary::kCallOnSlowPath
1968 : LocationSummary::kNoCall;
1969 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind);
1970 locations->SetInAt(0, Location::RequiresRegister());
1971 locations->SetInAt(1, Location::RequiresRegister());
1972 if (instruction->HasUses()) {
1973 locations->SetOut(Location::SameAsFirstInput());
1974 }
1975 }
1976
VisitBoundsCheck(HBoundsCheck * instruction)1977 void InstructionCodeGeneratorMIPS::VisitBoundsCheck(HBoundsCheck* instruction) {
1978 LocationSummary* locations = instruction->GetLocations();
1979 BoundsCheckSlowPathMIPS* slow_path =
1980 new (GetGraph()->GetArena()) BoundsCheckSlowPathMIPS(instruction);
1981 codegen_->AddSlowPath(slow_path);
1982
1983 Register index = locations->InAt(0).AsRegister<Register>();
1984 Register length = locations->InAt(1).AsRegister<Register>();
1985
1986 // length is limited by the maximum positive signed 32-bit integer.
1987 // Unsigned comparison of length and index checks for index < 0
1988 // and for length <= index simultaneously.
1989 __ Bgeu(index, length, slow_path->GetEntryLabel());
1990 }
1991
VisitCheckCast(HCheckCast * instruction)1992 void LocationsBuilderMIPS::VisitCheckCast(HCheckCast* instruction) {
1993 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
1994 instruction,
1995 LocationSummary::kCallOnSlowPath);
1996 locations->SetInAt(0, Location::RequiresRegister());
1997 locations->SetInAt(1, Location::RequiresRegister());
1998 // Note that TypeCheckSlowPathMIPS uses this register too.
1999 locations->AddTemp(Location::RequiresRegister());
2000 }
2001
VisitCheckCast(HCheckCast * instruction)2002 void InstructionCodeGeneratorMIPS::VisitCheckCast(HCheckCast* instruction) {
2003 LocationSummary* locations = instruction->GetLocations();
2004 Register obj = locations->InAt(0).AsRegister<Register>();
2005 Register cls = locations->InAt(1).AsRegister<Register>();
2006 Register obj_cls = locations->GetTemp(0).AsRegister<Register>();
2007
2008 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) TypeCheckSlowPathMIPS(instruction);
2009 codegen_->AddSlowPath(slow_path);
2010
2011 // TODO: avoid this check if we know obj is not null.
2012 __ Beqz(obj, slow_path->GetExitLabel());
2013 // Compare the class of `obj` with `cls`.
2014 __ LoadFromOffset(kLoadWord, obj_cls, obj, mirror::Object::ClassOffset().Int32Value());
2015 __ Bne(obj_cls, cls, slow_path->GetEntryLabel());
2016 __ Bind(slow_path->GetExitLabel());
2017 }
2018
VisitClinitCheck(HClinitCheck * check)2019 void LocationsBuilderMIPS::VisitClinitCheck(HClinitCheck* check) {
2020 LocationSummary* locations =
2021 new (GetGraph()->GetArena()) LocationSummary(check, LocationSummary::kCallOnSlowPath);
2022 locations->SetInAt(0, Location::RequiresRegister());
2023 if (check->HasUses()) {
2024 locations->SetOut(Location::SameAsFirstInput());
2025 }
2026 }
2027
VisitClinitCheck(HClinitCheck * check)2028 void InstructionCodeGeneratorMIPS::VisitClinitCheck(HClinitCheck* check) {
2029 // We assume the class is not null.
2030 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) LoadClassSlowPathMIPS(
2031 check->GetLoadClass(),
2032 check,
2033 check->GetDexPc(),
2034 true);
2035 codegen_->AddSlowPath(slow_path);
2036 GenerateClassInitializationCheck(slow_path,
2037 check->GetLocations()->InAt(0).AsRegister<Register>());
2038 }
2039
VisitCompare(HCompare * compare)2040 void LocationsBuilderMIPS::VisitCompare(HCompare* compare) {
2041 Primitive::Type in_type = compare->InputAt(0)->GetType();
2042
2043 LocationSummary* locations =
2044 new (GetGraph()->GetArena()) LocationSummary(compare, LocationSummary::kNoCall);
2045
2046 switch (in_type) {
2047 case Primitive::kPrimBoolean:
2048 case Primitive::kPrimByte:
2049 case Primitive::kPrimShort:
2050 case Primitive::kPrimChar:
2051 case Primitive::kPrimInt:
2052 case Primitive::kPrimLong:
2053 locations->SetInAt(0, Location::RequiresRegister());
2054 locations->SetInAt(1, Location::RequiresRegister());
2055 // Output overlaps because it is written before doing the low comparison.
2056 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap);
2057 break;
2058
2059 case Primitive::kPrimFloat:
2060 case Primitive::kPrimDouble:
2061 locations->SetInAt(0, Location::RequiresFpuRegister());
2062 locations->SetInAt(1, Location::RequiresFpuRegister());
2063 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
2064 break;
2065
2066 default:
2067 LOG(FATAL) << "Unexpected type for compare operation " << in_type;
2068 }
2069 }
2070
VisitCompare(HCompare * instruction)2071 void InstructionCodeGeneratorMIPS::VisitCompare(HCompare* instruction) {
2072 LocationSummary* locations = instruction->GetLocations();
2073 Register res = locations->Out().AsRegister<Register>();
2074 Primitive::Type in_type = instruction->InputAt(0)->GetType();
2075 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
2076
2077 // 0 if: left == right
2078 // 1 if: left > right
2079 // -1 if: left < right
2080 switch (in_type) {
2081 case Primitive::kPrimBoolean:
2082 case Primitive::kPrimByte:
2083 case Primitive::kPrimShort:
2084 case Primitive::kPrimChar:
2085 case Primitive::kPrimInt: {
2086 Register lhs = locations->InAt(0).AsRegister<Register>();
2087 Register rhs = locations->InAt(1).AsRegister<Register>();
2088 __ Slt(TMP, lhs, rhs);
2089 __ Slt(res, rhs, lhs);
2090 __ Subu(res, res, TMP);
2091 break;
2092 }
2093 case Primitive::kPrimLong: {
2094 MipsLabel done;
2095 Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
2096 Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
2097 Register rhs_high = locations->InAt(1).AsRegisterPairHigh<Register>();
2098 Register rhs_low = locations->InAt(1).AsRegisterPairLow<Register>();
2099 // TODO: more efficient (direct) comparison with a constant.
2100 __ Slt(TMP, lhs_high, rhs_high);
2101 __ Slt(AT, rhs_high, lhs_high); // Inverted: is actually gt.
2102 __ Subu(res, AT, TMP); // Result -1:1:0 for [ <, >, == ].
2103 __ Bnez(res, &done); // If we compared ==, check if lower bits are also equal.
2104 __ Sltu(TMP, lhs_low, rhs_low);
2105 __ Sltu(AT, rhs_low, lhs_low); // Inverted: is actually gt.
2106 __ Subu(res, AT, TMP); // Result -1:1:0 for [ <, >, == ].
2107 __ Bind(&done);
2108 break;
2109 }
2110
2111 case Primitive::kPrimFloat: {
2112 bool gt_bias = instruction->IsGtBias();
2113 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
2114 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
2115 MipsLabel done;
2116 if (isR6) {
2117 __ CmpEqS(FTMP, lhs, rhs);
2118 __ LoadConst32(res, 0);
2119 __ Bc1nez(FTMP, &done);
2120 if (gt_bias) {
2121 __ CmpLtS(FTMP, lhs, rhs);
2122 __ LoadConst32(res, -1);
2123 __ Bc1nez(FTMP, &done);
2124 __ LoadConst32(res, 1);
2125 } else {
2126 __ CmpLtS(FTMP, rhs, lhs);
2127 __ LoadConst32(res, 1);
2128 __ Bc1nez(FTMP, &done);
2129 __ LoadConst32(res, -1);
2130 }
2131 } else {
2132 if (gt_bias) {
2133 __ ColtS(0, lhs, rhs);
2134 __ LoadConst32(res, -1);
2135 __ Bc1t(0, &done);
2136 __ CeqS(0, lhs, rhs);
2137 __ LoadConst32(res, 1);
2138 __ Movt(res, ZERO, 0);
2139 } else {
2140 __ ColtS(0, rhs, lhs);
2141 __ LoadConst32(res, 1);
2142 __ Bc1t(0, &done);
2143 __ CeqS(0, lhs, rhs);
2144 __ LoadConst32(res, -1);
2145 __ Movt(res, ZERO, 0);
2146 }
2147 }
2148 __ Bind(&done);
2149 break;
2150 }
2151 case Primitive::kPrimDouble: {
2152 bool gt_bias = instruction->IsGtBias();
2153 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
2154 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
2155 MipsLabel done;
2156 if (isR6) {
2157 __ CmpEqD(FTMP, lhs, rhs);
2158 __ LoadConst32(res, 0);
2159 __ Bc1nez(FTMP, &done);
2160 if (gt_bias) {
2161 __ CmpLtD(FTMP, lhs, rhs);
2162 __ LoadConst32(res, -1);
2163 __ Bc1nez(FTMP, &done);
2164 __ LoadConst32(res, 1);
2165 } else {
2166 __ CmpLtD(FTMP, rhs, lhs);
2167 __ LoadConst32(res, 1);
2168 __ Bc1nez(FTMP, &done);
2169 __ LoadConst32(res, -1);
2170 }
2171 } else {
2172 if (gt_bias) {
2173 __ ColtD(0, lhs, rhs);
2174 __ LoadConst32(res, -1);
2175 __ Bc1t(0, &done);
2176 __ CeqD(0, lhs, rhs);
2177 __ LoadConst32(res, 1);
2178 __ Movt(res, ZERO, 0);
2179 } else {
2180 __ ColtD(0, rhs, lhs);
2181 __ LoadConst32(res, 1);
2182 __ Bc1t(0, &done);
2183 __ CeqD(0, lhs, rhs);
2184 __ LoadConst32(res, -1);
2185 __ Movt(res, ZERO, 0);
2186 }
2187 }
2188 __ Bind(&done);
2189 break;
2190 }
2191
2192 default:
2193 LOG(FATAL) << "Unimplemented compare type " << in_type;
2194 }
2195 }
2196
HandleCondition(HCondition * instruction)2197 void LocationsBuilderMIPS::HandleCondition(HCondition* instruction) {
2198 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
2199 switch (instruction->InputAt(0)->GetType()) {
2200 default:
2201 case Primitive::kPrimLong:
2202 locations->SetInAt(0, Location::RequiresRegister());
2203 locations->SetInAt(1, Location::RegisterOrConstant(instruction->InputAt(1)));
2204 break;
2205
2206 case Primitive::kPrimFloat:
2207 case Primitive::kPrimDouble:
2208 locations->SetInAt(0, Location::RequiresFpuRegister());
2209 locations->SetInAt(1, Location::RequiresFpuRegister());
2210 break;
2211 }
2212 if (!instruction->IsEmittedAtUseSite()) {
2213 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
2214 }
2215 }
2216
HandleCondition(HCondition * instruction)2217 void InstructionCodeGeneratorMIPS::HandleCondition(HCondition* instruction) {
2218 if (instruction->IsEmittedAtUseSite()) {
2219 return;
2220 }
2221
2222 Primitive::Type type = instruction->InputAt(0)->GetType();
2223 LocationSummary* locations = instruction->GetLocations();
2224 Register dst = locations->Out().AsRegister<Register>();
2225 MipsLabel true_label;
2226
2227 switch (type) {
2228 default:
2229 // Integer case.
2230 GenerateIntCompare(instruction->GetCondition(), locations);
2231 return;
2232
2233 case Primitive::kPrimLong:
2234 // TODO: don't use branches.
2235 GenerateLongCompareAndBranch(instruction->GetCondition(), locations, &true_label);
2236 break;
2237
2238 case Primitive::kPrimFloat:
2239 case Primitive::kPrimDouble:
2240 // TODO: don't use branches.
2241 GenerateFpCompareAndBranch(instruction->GetCondition(),
2242 instruction->IsGtBias(),
2243 type,
2244 locations,
2245 &true_label);
2246 break;
2247 }
2248
2249 // Convert the branches into the result.
2250 MipsLabel done;
2251
2252 // False case: result = 0.
2253 __ LoadConst32(dst, 0);
2254 __ B(&done);
2255
2256 // True case: result = 1.
2257 __ Bind(&true_label);
2258 __ LoadConst32(dst, 1);
2259 __ Bind(&done);
2260 }
2261
DivRemOneOrMinusOne(HBinaryOperation * instruction)2262 void InstructionCodeGeneratorMIPS::DivRemOneOrMinusOne(HBinaryOperation* instruction) {
2263 DCHECK(instruction->IsDiv() || instruction->IsRem());
2264 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
2265
2266 LocationSummary* locations = instruction->GetLocations();
2267 Location second = locations->InAt(1);
2268 DCHECK(second.IsConstant());
2269
2270 Register out = locations->Out().AsRegister<Register>();
2271 Register dividend = locations->InAt(0).AsRegister<Register>();
2272 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue();
2273 DCHECK(imm == 1 || imm == -1);
2274
2275 if (instruction->IsRem()) {
2276 __ Move(out, ZERO);
2277 } else {
2278 if (imm == -1) {
2279 __ Subu(out, ZERO, dividend);
2280 } else if (out != dividend) {
2281 __ Move(out, dividend);
2282 }
2283 }
2284 }
2285
DivRemByPowerOfTwo(HBinaryOperation * instruction)2286 void InstructionCodeGeneratorMIPS::DivRemByPowerOfTwo(HBinaryOperation* instruction) {
2287 DCHECK(instruction->IsDiv() || instruction->IsRem());
2288 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
2289
2290 LocationSummary* locations = instruction->GetLocations();
2291 Location second = locations->InAt(1);
2292 DCHECK(second.IsConstant());
2293
2294 Register out = locations->Out().AsRegister<Register>();
2295 Register dividend = locations->InAt(0).AsRegister<Register>();
2296 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue();
2297 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm));
2298 int ctz_imm = CTZ(abs_imm);
2299
2300 if (instruction->IsDiv()) {
2301 if (ctz_imm == 1) {
2302 // Fast path for division by +/-2, which is very common.
2303 __ Srl(TMP, dividend, 31);
2304 } else {
2305 __ Sra(TMP, dividend, 31);
2306 __ Srl(TMP, TMP, 32 - ctz_imm);
2307 }
2308 __ Addu(out, dividend, TMP);
2309 __ Sra(out, out, ctz_imm);
2310 if (imm < 0) {
2311 __ Subu(out, ZERO, out);
2312 }
2313 } else {
2314 if (ctz_imm == 1) {
2315 // Fast path for modulo +/-2, which is very common.
2316 __ Sra(TMP, dividend, 31);
2317 __ Subu(out, dividend, TMP);
2318 __ Andi(out, out, 1);
2319 __ Addu(out, out, TMP);
2320 } else {
2321 __ Sra(TMP, dividend, 31);
2322 __ Srl(TMP, TMP, 32 - ctz_imm);
2323 __ Addu(out, dividend, TMP);
2324 if (IsUint<16>(abs_imm - 1)) {
2325 __ Andi(out, out, abs_imm - 1);
2326 } else {
2327 __ Sll(out, out, 32 - ctz_imm);
2328 __ Srl(out, out, 32 - ctz_imm);
2329 }
2330 __ Subu(out, out, TMP);
2331 }
2332 }
2333 }
2334
GenerateDivRemWithAnyConstant(HBinaryOperation * instruction)2335 void InstructionCodeGeneratorMIPS::GenerateDivRemWithAnyConstant(HBinaryOperation* instruction) {
2336 DCHECK(instruction->IsDiv() || instruction->IsRem());
2337 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
2338
2339 LocationSummary* locations = instruction->GetLocations();
2340 Location second = locations->InAt(1);
2341 DCHECK(second.IsConstant());
2342
2343 Register out = locations->Out().AsRegister<Register>();
2344 Register dividend = locations->InAt(0).AsRegister<Register>();
2345 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue();
2346
2347 int64_t magic;
2348 int shift;
2349 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift);
2350
2351 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
2352
2353 __ LoadConst32(TMP, magic);
2354 if (isR6) {
2355 __ MuhR6(TMP, dividend, TMP);
2356 } else {
2357 __ MultR2(dividend, TMP);
2358 __ Mfhi(TMP);
2359 }
2360 if (imm > 0 && magic < 0) {
2361 __ Addu(TMP, TMP, dividend);
2362 } else if (imm < 0 && magic > 0) {
2363 __ Subu(TMP, TMP, dividend);
2364 }
2365
2366 if (shift != 0) {
2367 __ Sra(TMP, TMP, shift);
2368 }
2369
2370 if (instruction->IsDiv()) {
2371 __ Sra(out, TMP, 31);
2372 __ Subu(out, TMP, out);
2373 } else {
2374 __ Sra(AT, TMP, 31);
2375 __ Subu(AT, TMP, AT);
2376 __ LoadConst32(TMP, imm);
2377 if (isR6) {
2378 __ MulR6(TMP, AT, TMP);
2379 } else {
2380 __ MulR2(TMP, AT, TMP);
2381 }
2382 __ Subu(out, dividend, TMP);
2383 }
2384 }
2385
GenerateDivRemIntegral(HBinaryOperation * instruction)2386 void InstructionCodeGeneratorMIPS::GenerateDivRemIntegral(HBinaryOperation* instruction) {
2387 DCHECK(instruction->IsDiv() || instruction->IsRem());
2388 DCHECK_EQ(instruction->GetResultType(), Primitive::kPrimInt);
2389
2390 LocationSummary* locations = instruction->GetLocations();
2391 Register out = locations->Out().AsRegister<Register>();
2392 Location second = locations->InAt(1);
2393
2394 if (second.IsConstant()) {
2395 int32_t imm = second.GetConstant()->AsIntConstant()->GetValue();
2396 if (imm == 0) {
2397 // Do not generate anything. DivZeroCheck would prevent any code to be executed.
2398 } else if (imm == 1 || imm == -1) {
2399 DivRemOneOrMinusOne(instruction);
2400 } else if (IsPowerOfTwo(AbsOrMin(imm))) {
2401 DivRemByPowerOfTwo(instruction);
2402 } else {
2403 DCHECK(imm <= -2 || imm >= 2);
2404 GenerateDivRemWithAnyConstant(instruction);
2405 }
2406 } else {
2407 Register dividend = locations->InAt(0).AsRegister<Register>();
2408 Register divisor = second.AsRegister<Register>();
2409 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
2410 if (instruction->IsDiv()) {
2411 if (isR6) {
2412 __ DivR6(out, dividend, divisor);
2413 } else {
2414 __ DivR2(out, dividend, divisor);
2415 }
2416 } else {
2417 if (isR6) {
2418 __ ModR6(out, dividend, divisor);
2419 } else {
2420 __ ModR2(out, dividend, divisor);
2421 }
2422 }
2423 }
2424 }
2425
VisitDiv(HDiv * div)2426 void LocationsBuilderMIPS::VisitDiv(HDiv* div) {
2427 Primitive::Type type = div->GetResultType();
2428 LocationSummary::CallKind call_kind = (type == Primitive::kPrimLong)
2429 ? LocationSummary::kCall
2430 : LocationSummary::kNoCall;
2431
2432 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(div, call_kind);
2433
2434 switch (type) {
2435 case Primitive::kPrimInt:
2436 locations->SetInAt(0, Location::RequiresRegister());
2437 locations->SetInAt(1, Location::RegisterOrConstant(div->InputAt(1)));
2438 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
2439 break;
2440
2441 case Primitive::kPrimLong: {
2442 InvokeRuntimeCallingConvention calling_convention;
2443 locations->SetInAt(0, Location::RegisterPairLocation(
2444 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1)));
2445 locations->SetInAt(1, Location::RegisterPairLocation(
2446 calling_convention.GetRegisterAt(2), calling_convention.GetRegisterAt(3)));
2447 locations->SetOut(calling_convention.GetReturnLocation(type));
2448 break;
2449 }
2450
2451 case Primitive::kPrimFloat:
2452 case Primitive::kPrimDouble:
2453 locations->SetInAt(0, Location::RequiresFpuRegister());
2454 locations->SetInAt(1, Location::RequiresFpuRegister());
2455 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
2456 break;
2457
2458 default:
2459 LOG(FATAL) << "Unexpected div type " << type;
2460 }
2461 }
2462
VisitDiv(HDiv * instruction)2463 void InstructionCodeGeneratorMIPS::VisitDiv(HDiv* instruction) {
2464 Primitive::Type type = instruction->GetType();
2465 LocationSummary* locations = instruction->GetLocations();
2466
2467 switch (type) {
2468 case Primitive::kPrimInt:
2469 GenerateDivRemIntegral(instruction);
2470 break;
2471 case Primitive::kPrimLong: {
2472 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pLdiv),
2473 instruction,
2474 instruction->GetDexPc(),
2475 nullptr,
2476 IsDirectEntrypoint(kQuickLdiv));
2477 CheckEntrypointTypes<kQuickLdiv, int64_t, int64_t, int64_t>();
2478 break;
2479 }
2480 case Primitive::kPrimFloat:
2481 case Primitive::kPrimDouble: {
2482 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
2483 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
2484 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
2485 if (type == Primitive::kPrimFloat) {
2486 __ DivS(dst, lhs, rhs);
2487 } else {
2488 __ DivD(dst, lhs, rhs);
2489 }
2490 break;
2491 }
2492 default:
2493 LOG(FATAL) << "Unexpected div type " << type;
2494 }
2495 }
2496
VisitDivZeroCheck(HDivZeroCheck * instruction)2497 void LocationsBuilderMIPS::VisitDivZeroCheck(HDivZeroCheck* instruction) {
2498 LocationSummary::CallKind call_kind = instruction->CanThrowIntoCatchBlock()
2499 ? LocationSummary::kCallOnSlowPath
2500 : LocationSummary::kNoCall;
2501 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind);
2502 locations->SetInAt(0, Location::RegisterOrConstant(instruction->InputAt(0)));
2503 if (instruction->HasUses()) {
2504 locations->SetOut(Location::SameAsFirstInput());
2505 }
2506 }
2507
VisitDivZeroCheck(HDivZeroCheck * instruction)2508 void InstructionCodeGeneratorMIPS::VisitDivZeroCheck(HDivZeroCheck* instruction) {
2509 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) DivZeroCheckSlowPathMIPS(instruction);
2510 codegen_->AddSlowPath(slow_path);
2511 Location value = instruction->GetLocations()->InAt(0);
2512 Primitive::Type type = instruction->GetType();
2513
2514 switch (type) {
2515 case Primitive::kPrimBoolean:
2516 case Primitive::kPrimByte:
2517 case Primitive::kPrimChar:
2518 case Primitive::kPrimShort:
2519 case Primitive::kPrimInt: {
2520 if (value.IsConstant()) {
2521 if (value.GetConstant()->AsIntConstant()->GetValue() == 0) {
2522 __ B(slow_path->GetEntryLabel());
2523 } else {
2524 // A division by a non-null constant is valid. We don't need to perform
2525 // any check, so simply fall through.
2526 }
2527 } else {
2528 DCHECK(value.IsRegister()) << value;
2529 __ Beqz(value.AsRegister<Register>(), slow_path->GetEntryLabel());
2530 }
2531 break;
2532 }
2533 case Primitive::kPrimLong: {
2534 if (value.IsConstant()) {
2535 if (value.GetConstant()->AsLongConstant()->GetValue() == 0) {
2536 __ B(slow_path->GetEntryLabel());
2537 } else {
2538 // A division by a non-null constant is valid. We don't need to perform
2539 // any check, so simply fall through.
2540 }
2541 } else {
2542 DCHECK(value.IsRegisterPair()) << value;
2543 __ Or(TMP, value.AsRegisterPairHigh<Register>(), value.AsRegisterPairLow<Register>());
2544 __ Beqz(TMP, slow_path->GetEntryLabel());
2545 }
2546 break;
2547 }
2548 default:
2549 LOG(FATAL) << "Unexpected type " << type << " for DivZeroCheck.";
2550 }
2551 }
2552
VisitDoubleConstant(HDoubleConstant * constant)2553 void LocationsBuilderMIPS::VisitDoubleConstant(HDoubleConstant* constant) {
2554 LocationSummary* locations =
2555 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall);
2556 locations->SetOut(Location::ConstantLocation(constant));
2557 }
2558
VisitDoubleConstant(HDoubleConstant * cst ATTRIBUTE_UNUSED)2559 void InstructionCodeGeneratorMIPS::VisitDoubleConstant(HDoubleConstant* cst ATTRIBUTE_UNUSED) {
2560 // Will be generated at use site.
2561 }
2562
VisitExit(HExit * exit)2563 void LocationsBuilderMIPS::VisitExit(HExit* exit) {
2564 exit->SetLocations(nullptr);
2565 }
2566
VisitExit(HExit * exit ATTRIBUTE_UNUSED)2567 void InstructionCodeGeneratorMIPS::VisitExit(HExit* exit ATTRIBUTE_UNUSED) {
2568 }
2569
VisitFloatConstant(HFloatConstant * constant)2570 void LocationsBuilderMIPS::VisitFloatConstant(HFloatConstant* constant) {
2571 LocationSummary* locations =
2572 new (GetGraph()->GetArena()) LocationSummary(constant, LocationSummary::kNoCall);
2573 locations->SetOut(Location::ConstantLocation(constant));
2574 }
2575
VisitFloatConstant(HFloatConstant * constant ATTRIBUTE_UNUSED)2576 void InstructionCodeGeneratorMIPS::VisitFloatConstant(HFloatConstant* constant ATTRIBUTE_UNUSED) {
2577 // Will be generated at use site.
2578 }
2579
VisitGoto(HGoto * got)2580 void LocationsBuilderMIPS::VisitGoto(HGoto* got) {
2581 got->SetLocations(nullptr);
2582 }
2583
HandleGoto(HInstruction * got,HBasicBlock * successor)2584 void InstructionCodeGeneratorMIPS::HandleGoto(HInstruction* got, HBasicBlock* successor) {
2585 DCHECK(!successor->IsExitBlock());
2586 HBasicBlock* block = got->GetBlock();
2587 HInstruction* previous = got->GetPrevious();
2588 HLoopInformation* info = block->GetLoopInformation();
2589
2590 if (info != nullptr && info->IsBackEdge(*block) && info->HasSuspendCheck()) {
2591 codegen_->ClearSpillSlotsFromLoopPhisInStackMap(info->GetSuspendCheck());
2592 GenerateSuspendCheck(info->GetSuspendCheck(), successor);
2593 return;
2594 }
2595 if (block->IsEntryBlock() && (previous != nullptr) && previous->IsSuspendCheck()) {
2596 GenerateSuspendCheck(previous->AsSuspendCheck(), nullptr);
2597 }
2598 if (!codegen_->GoesToNextBlock(block, successor)) {
2599 __ B(codegen_->GetLabelOf(successor));
2600 }
2601 }
2602
VisitGoto(HGoto * got)2603 void InstructionCodeGeneratorMIPS::VisitGoto(HGoto* got) {
2604 HandleGoto(got, got->GetSuccessor());
2605 }
2606
VisitTryBoundary(HTryBoundary * try_boundary)2607 void LocationsBuilderMIPS::VisitTryBoundary(HTryBoundary* try_boundary) {
2608 try_boundary->SetLocations(nullptr);
2609 }
2610
VisitTryBoundary(HTryBoundary * try_boundary)2611 void InstructionCodeGeneratorMIPS::VisitTryBoundary(HTryBoundary* try_boundary) {
2612 HBasicBlock* successor = try_boundary->GetNormalFlowSuccessor();
2613 if (!successor->IsExitBlock()) {
2614 HandleGoto(try_boundary, successor);
2615 }
2616 }
2617
GenerateIntCompare(IfCondition cond,LocationSummary * locations)2618 void InstructionCodeGeneratorMIPS::GenerateIntCompare(IfCondition cond,
2619 LocationSummary* locations) {
2620 Register dst = locations->Out().AsRegister<Register>();
2621 Register lhs = locations->InAt(0).AsRegister<Register>();
2622 Location rhs_location = locations->InAt(1);
2623 Register rhs_reg = ZERO;
2624 int64_t rhs_imm = 0;
2625 bool use_imm = rhs_location.IsConstant();
2626 if (use_imm) {
2627 rhs_imm = CodeGenerator::GetInt32ValueOf(rhs_location.GetConstant());
2628 } else {
2629 rhs_reg = rhs_location.AsRegister<Register>();
2630 }
2631
2632 switch (cond) {
2633 case kCondEQ:
2634 case kCondNE:
2635 if (use_imm && IsUint<16>(rhs_imm)) {
2636 __ Xori(dst, lhs, rhs_imm);
2637 } else {
2638 if (use_imm) {
2639 rhs_reg = TMP;
2640 __ LoadConst32(rhs_reg, rhs_imm);
2641 }
2642 __ Xor(dst, lhs, rhs_reg);
2643 }
2644 if (cond == kCondEQ) {
2645 __ Sltiu(dst, dst, 1);
2646 } else {
2647 __ Sltu(dst, ZERO, dst);
2648 }
2649 break;
2650
2651 case kCondLT:
2652 case kCondGE:
2653 if (use_imm && IsInt<16>(rhs_imm)) {
2654 __ Slti(dst, lhs, rhs_imm);
2655 } else {
2656 if (use_imm) {
2657 rhs_reg = TMP;
2658 __ LoadConst32(rhs_reg, rhs_imm);
2659 }
2660 __ Slt(dst, lhs, rhs_reg);
2661 }
2662 if (cond == kCondGE) {
2663 // Simulate lhs >= rhs via !(lhs < rhs) since there's
2664 // only the slt instruction but no sge.
2665 __ Xori(dst, dst, 1);
2666 }
2667 break;
2668
2669 case kCondLE:
2670 case kCondGT:
2671 if (use_imm && IsInt<16>(rhs_imm + 1)) {
2672 // Simulate lhs <= rhs via lhs < rhs + 1.
2673 __ Slti(dst, lhs, rhs_imm + 1);
2674 if (cond == kCondGT) {
2675 // Simulate lhs > rhs via !(lhs <= rhs) since there's
2676 // only the slti instruction but no sgti.
2677 __ Xori(dst, dst, 1);
2678 }
2679 } else {
2680 if (use_imm) {
2681 rhs_reg = TMP;
2682 __ LoadConst32(rhs_reg, rhs_imm);
2683 }
2684 __ Slt(dst, rhs_reg, lhs);
2685 if (cond == kCondLE) {
2686 // Simulate lhs <= rhs via !(rhs < lhs) since there's
2687 // only the slt instruction but no sle.
2688 __ Xori(dst, dst, 1);
2689 }
2690 }
2691 break;
2692
2693 case kCondB:
2694 case kCondAE:
2695 if (use_imm && IsInt<16>(rhs_imm)) {
2696 // Sltiu sign-extends its 16-bit immediate operand before
2697 // the comparison and thus lets us compare directly with
2698 // unsigned values in the ranges [0, 0x7fff] and
2699 // [0xffff8000, 0xffffffff].
2700 __ Sltiu(dst, lhs, rhs_imm);
2701 } else {
2702 if (use_imm) {
2703 rhs_reg = TMP;
2704 __ LoadConst32(rhs_reg, rhs_imm);
2705 }
2706 __ Sltu(dst, lhs, rhs_reg);
2707 }
2708 if (cond == kCondAE) {
2709 // Simulate lhs >= rhs via !(lhs < rhs) since there's
2710 // only the sltu instruction but no sgeu.
2711 __ Xori(dst, dst, 1);
2712 }
2713 break;
2714
2715 case kCondBE:
2716 case kCondA:
2717 if (use_imm && (rhs_imm != -1) && IsInt<16>(rhs_imm + 1)) {
2718 // Simulate lhs <= rhs via lhs < rhs + 1.
2719 // Note that this only works if rhs + 1 does not overflow
2720 // to 0, hence the check above.
2721 // Sltiu sign-extends its 16-bit immediate operand before
2722 // the comparison and thus lets us compare directly with
2723 // unsigned values in the ranges [0, 0x7fff] and
2724 // [0xffff8000, 0xffffffff].
2725 __ Sltiu(dst, lhs, rhs_imm + 1);
2726 if (cond == kCondA) {
2727 // Simulate lhs > rhs via !(lhs <= rhs) since there's
2728 // only the sltiu instruction but no sgtiu.
2729 __ Xori(dst, dst, 1);
2730 }
2731 } else {
2732 if (use_imm) {
2733 rhs_reg = TMP;
2734 __ LoadConst32(rhs_reg, rhs_imm);
2735 }
2736 __ Sltu(dst, rhs_reg, lhs);
2737 if (cond == kCondBE) {
2738 // Simulate lhs <= rhs via !(rhs < lhs) since there's
2739 // only the sltu instruction but no sleu.
2740 __ Xori(dst, dst, 1);
2741 }
2742 }
2743 break;
2744 }
2745 }
2746
GenerateIntCompareAndBranch(IfCondition cond,LocationSummary * locations,MipsLabel * label)2747 void InstructionCodeGeneratorMIPS::GenerateIntCompareAndBranch(IfCondition cond,
2748 LocationSummary* locations,
2749 MipsLabel* label) {
2750 Register lhs = locations->InAt(0).AsRegister<Register>();
2751 Location rhs_location = locations->InAt(1);
2752 Register rhs_reg = ZERO;
2753 int32_t rhs_imm = 0;
2754 bool use_imm = rhs_location.IsConstant();
2755 if (use_imm) {
2756 rhs_imm = CodeGenerator::GetInt32ValueOf(rhs_location.GetConstant());
2757 } else {
2758 rhs_reg = rhs_location.AsRegister<Register>();
2759 }
2760
2761 if (use_imm && rhs_imm == 0) {
2762 switch (cond) {
2763 case kCondEQ:
2764 case kCondBE: // <= 0 if zero
2765 __ Beqz(lhs, label);
2766 break;
2767 case kCondNE:
2768 case kCondA: // > 0 if non-zero
2769 __ Bnez(lhs, label);
2770 break;
2771 case kCondLT:
2772 __ Bltz(lhs, label);
2773 break;
2774 case kCondGE:
2775 __ Bgez(lhs, label);
2776 break;
2777 case kCondLE:
2778 __ Blez(lhs, label);
2779 break;
2780 case kCondGT:
2781 __ Bgtz(lhs, label);
2782 break;
2783 case kCondB: // always false
2784 break;
2785 case kCondAE: // always true
2786 __ B(label);
2787 break;
2788 }
2789 } else {
2790 if (use_imm) {
2791 // TODO: more efficient comparison with 16-bit constants without loading them into TMP.
2792 rhs_reg = TMP;
2793 __ LoadConst32(rhs_reg, rhs_imm);
2794 }
2795 switch (cond) {
2796 case kCondEQ:
2797 __ Beq(lhs, rhs_reg, label);
2798 break;
2799 case kCondNE:
2800 __ Bne(lhs, rhs_reg, label);
2801 break;
2802 case kCondLT:
2803 __ Blt(lhs, rhs_reg, label);
2804 break;
2805 case kCondGE:
2806 __ Bge(lhs, rhs_reg, label);
2807 break;
2808 case kCondLE:
2809 __ Bge(rhs_reg, lhs, label);
2810 break;
2811 case kCondGT:
2812 __ Blt(rhs_reg, lhs, label);
2813 break;
2814 case kCondB:
2815 __ Bltu(lhs, rhs_reg, label);
2816 break;
2817 case kCondAE:
2818 __ Bgeu(lhs, rhs_reg, label);
2819 break;
2820 case kCondBE:
2821 __ Bgeu(rhs_reg, lhs, label);
2822 break;
2823 case kCondA:
2824 __ Bltu(rhs_reg, lhs, label);
2825 break;
2826 }
2827 }
2828 }
2829
GenerateLongCompareAndBranch(IfCondition cond,LocationSummary * locations,MipsLabel * label)2830 void InstructionCodeGeneratorMIPS::GenerateLongCompareAndBranch(IfCondition cond,
2831 LocationSummary* locations,
2832 MipsLabel* label) {
2833 Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
2834 Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
2835 Location rhs_location = locations->InAt(1);
2836 Register rhs_high = ZERO;
2837 Register rhs_low = ZERO;
2838 int64_t imm = 0;
2839 uint32_t imm_high = 0;
2840 uint32_t imm_low = 0;
2841 bool use_imm = rhs_location.IsConstant();
2842 if (use_imm) {
2843 imm = rhs_location.GetConstant()->AsLongConstant()->GetValue();
2844 imm_high = High32Bits(imm);
2845 imm_low = Low32Bits(imm);
2846 } else {
2847 rhs_high = rhs_location.AsRegisterPairHigh<Register>();
2848 rhs_low = rhs_location.AsRegisterPairLow<Register>();
2849 }
2850
2851 if (use_imm && imm == 0) {
2852 switch (cond) {
2853 case kCondEQ:
2854 case kCondBE: // <= 0 if zero
2855 __ Or(TMP, lhs_high, lhs_low);
2856 __ Beqz(TMP, label);
2857 break;
2858 case kCondNE:
2859 case kCondA: // > 0 if non-zero
2860 __ Or(TMP, lhs_high, lhs_low);
2861 __ Bnez(TMP, label);
2862 break;
2863 case kCondLT:
2864 __ Bltz(lhs_high, label);
2865 break;
2866 case kCondGE:
2867 __ Bgez(lhs_high, label);
2868 break;
2869 case kCondLE:
2870 __ Or(TMP, lhs_high, lhs_low);
2871 __ Sra(AT, lhs_high, 31);
2872 __ Bgeu(AT, TMP, label);
2873 break;
2874 case kCondGT:
2875 __ Or(TMP, lhs_high, lhs_low);
2876 __ Sra(AT, lhs_high, 31);
2877 __ Bltu(AT, TMP, label);
2878 break;
2879 case kCondB: // always false
2880 break;
2881 case kCondAE: // always true
2882 __ B(label);
2883 break;
2884 }
2885 } else if (use_imm) {
2886 // TODO: more efficient comparison with constants without loading them into TMP/AT.
2887 switch (cond) {
2888 case kCondEQ:
2889 __ LoadConst32(TMP, imm_high);
2890 __ Xor(TMP, TMP, lhs_high);
2891 __ LoadConst32(AT, imm_low);
2892 __ Xor(AT, AT, lhs_low);
2893 __ Or(TMP, TMP, AT);
2894 __ Beqz(TMP, label);
2895 break;
2896 case kCondNE:
2897 __ LoadConst32(TMP, imm_high);
2898 __ Xor(TMP, TMP, lhs_high);
2899 __ LoadConst32(AT, imm_low);
2900 __ Xor(AT, AT, lhs_low);
2901 __ Or(TMP, TMP, AT);
2902 __ Bnez(TMP, label);
2903 break;
2904 case kCondLT:
2905 __ LoadConst32(TMP, imm_high);
2906 __ Blt(lhs_high, TMP, label);
2907 __ Slt(TMP, TMP, lhs_high);
2908 __ LoadConst32(AT, imm_low);
2909 __ Sltu(AT, lhs_low, AT);
2910 __ Blt(TMP, AT, label);
2911 break;
2912 case kCondGE:
2913 __ LoadConst32(TMP, imm_high);
2914 __ Blt(TMP, lhs_high, label);
2915 __ Slt(TMP, lhs_high, TMP);
2916 __ LoadConst32(AT, imm_low);
2917 __ Sltu(AT, lhs_low, AT);
2918 __ Or(TMP, TMP, AT);
2919 __ Beqz(TMP, label);
2920 break;
2921 case kCondLE:
2922 __ LoadConst32(TMP, imm_high);
2923 __ Blt(lhs_high, TMP, label);
2924 __ Slt(TMP, TMP, lhs_high);
2925 __ LoadConst32(AT, imm_low);
2926 __ Sltu(AT, AT, lhs_low);
2927 __ Or(TMP, TMP, AT);
2928 __ Beqz(TMP, label);
2929 break;
2930 case kCondGT:
2931 __ LoadConst32(TMP, imm_high);
2932 __ Blt(TMP, lhs_high, label);
2933 __ Slt(TMP, lhs_high, TMP);
2934 __ LoadConst32(AT, imm_low);
2935 __ Sltu(AT, AT, lhs_low);
2936 __ Blt(TMP, AT, label);
2937 break;
2938 case kCondB:
2939 __ LoadConst32(TMP, imm_high);
2940 __ Bltu(lhs_high, TMP, label);
2941 __ Sltu(TMP, TMP, lhs_high);
2942 __ LoadConst32(AT, imm_low);
2943 __ Sltu(AT, lhs_low, AT);
2944 __ Blt(TMP, AT, label);
2945 break;
2946 case kCondAE:
2947 __ LoadConst32(TMP, imm_high);
2948 __ Bltu(TMP, lhs_high, label);
2949 __ Sltu(TMP, lhs_high, TMP);
2950 __ LoadConst32(AT, imm_low);
2951 __ Sltu(AT, lhs_low, AT);
2952 __ Or(TMP, TMP, AT);
2953 __ Beqz(TMP, label);
2954 break;
2955 case kCondBE:
2956 __ LoadConst32(TMP, imm_high);
2957 __ Bltu(lhs_high, TMP, label);
2958 __ Sltu(TMP, TMP, lhs_high);
2959 __ LoadConst32(AT, imm_low);
2960 __ Sltu(AT, AT, lhs_low);
2961 __ Or(TMP, TMP, AT);
2962 __ Beqz(TMP, label);
2963 break;
2964 case kCondA:
2965 __ LoadConst32(TMP, imm_high);
2966 __ Bltu(TMP, lhs_high, label);
2967 __ Sltu(TMP, lhs_high, TMP);
2968 __ LoadConst32(AT, imm_low);
2969 __ Sltu(AT, AT, lhs_low);
2970 __ Blt(TMP, AT, label);
2971 break;
2972 }
2973 } else {
2974 switch (cond) {
2975 case kCondEQ:
2976 __ Xor(TMP, lhs_high, rhs_high);
2977 __ Xor(AT, lhs_low, rhs_low);
2978 __ Or(TMP, TMP, AT);
2979 __ Beqz(TMP, label);
2980 break;
2981 case kCondNE:
2982 __ Xor(TMP, lhs_high, rhs_high);
2983 __ Xor(AT, lhs_low, rhs_low);
2984 __ Or(TMP, TMP, AT);
2985 __ Bnez(TMP, label);
2986 break;
2987 case kCondLT:
2988 __ Blt(lhs_high, rhs_high, label);
2989 __ Slt(TMP, rhs_high, lhs_high);
2990 __ Sltu(AT, lhs_low, rhs_low);
2991 __ Blt(TMP, AT, label);
2992 break;
2993 case kCondGE:
2994 __ Blt(rhs_high, lhs_high, label);
2995 __ Slt(TMP, lhs_high, rhs_high);
2996 __ Sltu(AT, lhs_low, rhs_low);
2997 __ Or(TMP, TMP, AT);
2998 __ Beqz(TMP, label);
2999 break;
3000 case kCondLE:
3001 __ Blt(lhs_high, rhs_high, label);
3002 __ Slt(TMP, rhs_high, lhs_high);
3003 __ Sltu(AT, rhs_low, lhs_low);
3004 __ Or(TMP, TMP, AT);
3005 __ Beqz(TMP, label);
3006 break;
3007 case kCondGT:
3008 __ Blt(rhs_high, lhs_high, label);
3009 __ Slt(TMP, lhs_high, rhs_high);
3010 __ Sltu(AT, rhs_low, lhs_low);
3011 __ Blt(TMP, AT, label);
3012 break;
3013 case kCondB:
3014 __ Bltu(lhs_high, rhs_high, label);
3015 __ Sltu(TMP, rhs_high, lhs_high);
3016 __ Sltu(AT, lhs_low, rhs_low);
3017 __ Blt(TMP, AT, label);
3018 break;
3019 case kCondAE:
3020 __ Bltu(rhs_high, lhs_high, label);
3021 __ Sltu(TMP, lhs_high, rhs_high);
3022 __ Sltu(AT, lhs_low, rhs_low);
3023 __ Or(TMP, TMP, AT);
3024 __ Beqz(TMP, label);
3025 break;
3026 case kCondBE:
3027 __ Bltu(lhs_high, rhs_high, label);
3028 __ Sltu(TMP, rhs_high, lhs_high);
3029 __ Sltu(AT, rhs_low, lhs_low);
3030 __ Or(TMP, TMP, AT);
3031 __ Beqz(TMP, label);
3032 break;
3033 case kCondA:
3034 __ Bltu(rhs_high, lhs_high, label);
3035 __ Sltu(TMP, lhs_high, rhs_high);
3036 __ Sltu(AT, rhs_low, lhs_low);
3037 __ Blt(TMP, AT, label);
3038 break;
3039 }
3040 }
3041 }
3042
GenerateFpCompareAndBranch(IfCondition cond,bool gt_bias,Primitive::Type type,LocationSummary * locations,MipsLabel * label)3043 void InstructionCodeGeneratorMIPS::GenerateFpCompareAndBranch(IfCondition cond,
3044 bool gt_bias,
3045 Primitive::Type type,
3046 LocationSummary* locations,
3047 MipsLabel* label) {
3048 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
3049 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
3050 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
3051 if (type == Primitive::kPrimFloat) {
3052 if (isR6) {
3053 switch (cond) {
3054 case kCondEQ:
3055 __ CmpEqS(FTMP, lhs, rhs);
3056 __ Bc1nez(FTMP, label);
3057 break;
3058 case kCondNE:
3059 __ CmpEqS(FTMP, lhs, rhs);
3060 __ Bc1eqz(FTMP, label);
3061 break;
3062 case kCondLT:
3063 if (gt_bias) {
3064 __ CmpLtS(FTMP, lhs, rhs);
3065 } else {
3066 __ CmpUltS(FTMP, lhs, rhs);
3067 }
3068 __ Bc1nez(FTMP, label);
3069 break;
3070 case kCondLE:
3071 if (gt_bias) {
3072 __ CmpLeS(FTMP, lhs, rhs);
3073 } else {
3074 __ CmpUleS(FTMP, lhs, rhs);
3075 }
3076 __ Bc1nez(FTMP, label);
3077 break;
3078 case kCondGT:
3079 if (gt_bias) {
3080 __ CmpUltS(FTMP, rhs, lhs);
3081 } else {
3082 __ CmpLtS(FTMP, rhs, lhs);
3083 }
3084 __ Bc1nez(FTMP, label);
3085 break;
3086 case kCondGE:
3087 if (gt_bias) {
3088 __ CmpUleS(FTMP, rhs, lhs);
3089 } else {
3090 __ CmpLeS(FTMP, rhs, lhs);
3091 }
3092 __ Bc1nez(FTMP, label);
3093 break;
3094 default:
3095 LOG(FATAL) << "Unexpected non-floating-point condition";
3096 }
3097 } else {
3098 switch (cond) {
3099 case kCondEQ:
3100 __ CeqS(0, lhs, rhs);
3101 __ Bc1t(0, label);
3102 break;
3103 case kCondNE:
3104 __ CeqS(0, lhs, rhs);
3105 __ Bc1f(0, label);
3106 break;
3107 case kCondLT:
3108 if (gt_bias) {
3109 __ ColtS(0, lhs, rhs);
3110 } else {
3111 __ CultS(0, lhs, rhs);
3112 }
3113 __ Bc1t(0, label);
3114 break;
3115 case kCondLE:
3116 if (gt_bias) {
3117 __ ColeS(0, lhs, rhs);
3118 } else {
3119 __ CuleS(0, lhs, rhs);
3120 }
3121 __ Bc1t(0, label);
3122 break;
3123 case kCondGT:
3124 if (gt_bias) {
3125 __ CultS(0, rhs, lhs);
3126 } else {
3127 __ ColtS(0, rhs, lhs);
3128 }
3129 __ Bc1t(0, label);
3130 break;
3131 case kCondGE:
3132 if (gt_bias) {
3133 __ CuleS(0, rhs, lhs);
3134 } else {
3135 __ ColeS(0, rhs, lhs);
3136 }
3137 __ Bc1t(0, label);
3138 break;
3139 default:
3140 LOG(FATAL) << "Unexpected non-floating-point condition";
3141 }
3142 }
3143 } else {
3144 DCHECK_EQ(type, Primitive::kPrimDouble);
3145 if (isR6) {
3146 switch (cond) {
3147 case kCondEQ:
3148 __ CmpEqD(FTMP, lhs, rhs);
3149 __ Bc1nez(FTMP, label);
3150 break;
3151 case kCondNE:
3152 __ CmpEqD(FTMP, lhs, rhs);
3153 __ Bc1eqz(FTMP, label);
3154 break;
3155 case kCondLT:
3156 if (gt_bias) {
3157 __ CmpLtD(FTMP, lhs, rhs);
3158 } else {
3159 __ CmpUltD(FTMP, lhs, rhs);
3160 }
3161 __ Bc1nez(FTMP, label);
3162 break;
3163 case kCondLE:
3164 if (gt_bias) {
3165 __ CmpLeD(FTMP, lhs, rhs);
3166 } else {
3167 __ CmpUleD(FTMP, lhs, rhs);
3168 }
3169 __ Bc1nez(FTMP, label);
3170 break;
3171 case kCondGT:
3172 if (gt_bias) {
3173 __ CmpUltD(FTMP, rhs, lhs);
3174 } else {
3175 __ CmpLtD(FTMP, rhs, lhs);
3176 }
3177 __ Bc1nez(FTMP, label);
3178 break;
3179 case kCondGE:
3180 if (gt_bias) {
3181 __ CmpUleD(FTMP, rhs, lhs);
3182 } else {
3183 __ CmpLeD(FTMP, rhs, lhs);
3184 }
3185 __ Bc1nez(FTMP, label);
3186 break;
3187 default:
3188 LOG(FATAL) << "Unexpected non-floating-point condition";
3189 }
3190 } else {
3191 switch (cond) {
3192 case kCondEQ:
3193 __ CeqD(0, lhs, rhs);
3194 __ Bc1t(0, label);
3195 break;
3196 case kCondNE:
3197 __ CeqD(0, lhs, rhs);
3198 __ Bc1f(0, label);
3199 break;
3200 case kCondLT:
3201 if (gt_bias) {
3202 __ ColtD(0, lhs, rhs);
3203 } else {
3204 __ CultD(0, lhs, rhs);
3205 }
3206 __ Bc1t(0, label);
3207 break;
3208 case kCondLE:
3209 if (gt_bias) {
3210 __ ColeD(0, lhs, rhs);
3211 } else {
3212 __ CuleD(0, lhs, rhs);
3213 }
3214 __ Bc1t(0, label);
3215 break;
3216 case kCondGT:
3217 if (gt_bias) {
3218 __ CultD(0, rhs, lhs);
3219 } else {
3220 __ ColtD(0, rhs, lhs);
3221 }
3222 __ Bc1t(0, label);
3223 break;
3224 case kCondGE:
3225 if (gt_bias) {
3226 __ CuleD(0, rhs, lhs);
3227 } else {
3228 __ ColeD(0, rhs, lhs);
3229 }
3230 __ Bc1t(0, label);
3231 break;
3232 default:
3233 LOG(FATAL) << "Unexpected non-floating-point condition";
3234 }
3235 }
3236 }
3237 }
3238
GenerateTestAndBranch(HInstruction * instruction,size_t condition_input_index,MipsLabel * true_target,MipsLabel * false_target)3239 void InstructionCodeGeneratorMIPS::GenerateTestAndBranch(HInstruction* instruction,
3240 size_t condition_input_index,
3241 MipsLabel* true_target,
3242 MipsLabel* false_target) {
3243 HInstruction* cond = instruction->InputAt(condition_input_index);
3244
3245 if (true_target == nullptr && false_target == nullptr) {
3246 // Nothing to do. The code always falls through.
3247 return;
3248 } else if (cond->IsIntConstant()) {
3249 // Constant condition, statically compared against "true" (integer value 1).
3250 if (cond->AsIntConstant()->IsTrue()) {
3251 if (true_target != nullptr) {
3252 __ B(true_target);
3253 }
3254 } else {
3255 DCHECK(cond->AsIntConstant()->IsFalse()) << cond->AsIntConstant()->GetValue();
3256 if (false_target != nullptr) {
3257 __ B(false_target);
3258 }
3259 }
3260 return;
3261 }
3262
3263 // The following code generates these patterns:
3264 // (1) true_target == nullptr && false_target != nullptr
3265 // - opposite condition true => branch to false_target
3266 // (2) true_target != nullptr && false_target == nullptr
3267 // - condition true => branch to true_target
3268 // (3) true_target != nullptr && false_target != nullptr
3269 // - condition true => branch to true_target
3270 // - branch to false_target
3271 if (IsBooleanValueOrMaterializedCondition(cond)) {
3272 // The condition instruction has been materialized, compare the output to 0.
3273 Location cond_val = instruction->GetLocations()->InAt(condition_input_index);
3274 DCHECK(cond_val.IsRegister());
3275 if (true_target == nullptr) {
3276 __ Beqz(cond_val.AsRegister<Register>(), false_target);
3277 } else {
3278 __ Bnez(cond_val.AsRegister<Register>(), true_target);
3279 }
3280 } else {
3281 // The condition instruction has not been materialized, use its inputs as
3282 // the comparison and its condition as the branch condition.
3283 HCondition* condition = cond->AsCondition();
3284 Primitive::Type type = condition->InputAt(0)->GetType();
3285 LocationSummary* locations = cond->GetLocations();
3286 IfCondition if_cond = condition->GetCondition();
3287 MipsLabel* branch_target = true_target;
3288
3289 if (true_target == nullptr) {
3290 if_cond = condition->GetOppositeCondition();
3291 branch_target = false_target;
3292 }
3293
3294 switch (type) {
3295 default:
3296 GenerateIntCompareAndBranch(if_cond, locations, branch_target);
3297 break;
3298 case Primitive::kPrimLong:
3299 GenerateLongCompareAndBranch(if_cond, locations, branch_target);
3300 break;
3301 case Primitive::kPrimFloat:
3302 case Primitive::kPrimDouble:
3303 GenerateFpCompareAndBranch(if_cond, condition->IsGtBias(), type, locations, branch_target);
3304 break;
3305 }
3306 }
3307
3308 // If neither branch falls through (case 3), the conditional branch to `true_target`
3309 // was already emitted (case 2) and we need to emit a jump to `false_target`.
3310 if (true_target != nullptr && false_target != nullptr) {
3311 __ B(false_target);
3312 }
3313 }
3314
VisitIf(HIf * if_instr)3315 void LocationsBuilderMIPS::VisitIf(HIf* if_instr) {
3316 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(if_instr);
3317 if (IsBooleanValueOrMaterializedCondition(if_instr->InputAt(0))) {
3318 locations->SetInAt(0, Location::RequiresRegister());
3319 }
3320 }
3321
VisitIf(HIf * if_instr)3322 void InstructionCodeGeneratorMIPS::VisitIf(HIf* if_instr) {
3323 HBasicBlock* true_successor = if_instr->IfTrueSuccessor();
3324 HBasicBlock* false_successor = if_instr->IfFalseSuccessor();
3325 MipsLabel* true_target = codegen_->GoesToNextBlock(if_instr->GetBlock(), true_successor) ?
3326 nullptr : codegen_->GetLabelOf(true_successor);
3327 MipsLabel* false_target = codegen_->GoesToNextBlock(if_instr->GetBlock(), false_successor) ?
3328 nullptr : codegen_->GetLabelOf(false_successor);
3329 GenerateTestAndBranch(if_instr, /* condition_input_index */ 0, true_target, false_target);
3330 }
3331
VisitDeoptimize(HDeoptimize * deoptimize)3332 void LocationsBuilderMIPS::VisitDeoptimize(HDeoptimize* deoptimize) {
3333 LocationSummary* locations = new (GetGraph()->GetArena())
3334 LocationSummary(deoptimize, LocationSummary::kCallOnSlowPath);
3335 if (IsBooleanValueOrMaterializedCondition(deoptimize->InputAt(0))) {
3336 locations->SetInAt(0, Location::RequiresRegister());
3337 }
3338 }
3339
VisitDeoptimize(HDeoptimize * deoptimize)3340 void InstructionCodeGeneratorMIPS::VisitDeoptimize(HDeoptimize* deoptimize) {
3341 SlowPathCodeMIPS* slow_path =
3342 deopt_slow_paths_.NewSlowPath<DeoptimizationSlowPathMIPS>(deoptimize);
3343 GenerateTestAndBranch(deoptimize,
3344 /* condition_input_index */ 0,
3345 slow_path->GetEntryLabel(),
3346 /* false_target */ nullptr);
3347 }
3348
VisitSelect(HSelect * select)3349 void LocationsBuilderMIPS::VisitSelect(HSelect* select) {
3350 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(select);
3351 if (Primitive::IsFloatingPointType(select->GetType())) {
3352 locations->SetInAt(0, Location::RequiresFpuRegister());
3353 locations->SetInAt(1, Location::RequiresFpuRegister());
3354 } else {
3355 locations->SetInAt(0, Location::RequiresRegister());
3356 locations->SetInAt(1, Location::RequiresRegister());
3357 }
3358 if (IsBooleanValueOrMaterializedCondition(select->GetCondition())) {
3359 locations->SetInAt(2, Location::RequiresRegister());
3360 }
3361 locations->SetOut(Location::SameAsFirstInput());
3362 }
3363
VisitSelect(HSelect * select)3364 void InstructionCodeGeneratorMIPS::VisitSelect(HSelect* select) {
3365 LocationSummary* locations = select->GetLocations();
3366 MipsLabel false_target;
3367 GenerateTestAndBranch(select,
3368 /* condition_input_index */ 2,
3369 /* true_target */ nullptr,
3370 &false_target);
3371 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType());
3372 __ Bind(&false_target);
3373 }
3374
VisitNativeDebugInfo(HNativeDebugInfo * info)3375 void LocationsBuilderMIPS::VisitNativeDebugInfo(HNativeDebugInfo* info) {
3376 new (GetGraph()->GetArena()) LocationSummary(info);
3377 }
3378
VisitNativeDebugInfo(HNativeDebugInfo *)3379 void InstructionCodeGeneratorMIPS::VisitNativeDebugInfo(HNativeDebugInfo*) {
3380 // MaybeRecordNativeDebugInfo is already called implicitly in CodeGenerator::Compile.
3381 }
3382
GenerateNop()3383 void CodeGeneratorMIPS::GenerateNop() {
3384 __ Nop();
3385 }
3386
HandleFieldGet(HInstruction * instruction,const FieldInfo & field_info)3387 void LocationsBuilderMIPS::HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info) {
3388 Primitive::Type field_type = field_info.GetFieldType();
3389 bool is_wide = (field_type == Primitive::kPrimLong) || (field_type == Primitive::kPrimDouble);
3390 bool generate_volatile = field_info.IsVolatile() && is_wide;
3391 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
3392 instruction, generate_volatile ? LocationSummary::kCall : LocationSummary::kNoCall);
3393
3394 locations->SetInAt(0, Location::RequiresRegister());
3395 if (generate_volatile) {
3396 InvokeRuntimeCallingConvention calling_convention;
3397 // need A0 to hold base + offset
3398 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
3399 if (field_type == Primitive::kPrimLong) {
3400 locations->SetOut(calling_convention.GetReturnLocation(Primitive::kPrimLong));
3401 } else {
3402 locations->SetOut(Location::RequiresFpuRegister());
3403 // Need some temp core regs since FP results are returned in core registers
3404 Location reg = calling_convention.GetReturnLocation(Primitive::kPrimLong);
3405 locations->AddTemp(Location::RegisterLocation(reg.AsRegisterPairLow<Register>()));
3406 locations->AddTemp(Location::RegisterLocation(reg.AsRegisterPairHigh<Register>()));
3407 }
3408 } else {
3409 if (Primitive::IsFloatingPointType(instruction->GetType())) {
3410 locations->SetOut(Location::RequiresFpuRegister());
3411 } else {
3412 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
3413 }
3414 }
3415 }
3416
HandleFieldGet(HInstruction * instruction,const FieldInfo & field_info,uint32_t dex_pc)3417 void InstructionCodeGeneratorMIPS::HandleFieldGet(HInstruction* instruction,
3418 const FieldInfo& field_info,
3419 uint32_t dex_pc) {
3420 Primitive::Type type = field_info.GetFieldType();
3421 LocationSummary* locations = instruction->GetLocations();
3422 Register obj = locations->InAt(0).AsRegister<Register>();
3423 LoadOperandType load_type = kLoadUnsignedByte;
3424 bool is_volatile = field_info.IsVolatile();
3425 uint32_t offset = field_info.GetFieldOffset().Uint32Value();
3426
3427 switch (type) {
3428 case Primitive::kPrimBoolean:
3429 load_type = kLoadUnsignedByte;
3430 break;
3431 case Primitive::kPrimByte:
3432 load_type = kLoadSignedByte;
3433 break;
3434 case Primitive::kPrimShort:
3435 load_type = kLoadSignedHalfword;
3436 break;
3437 case Primitive::kPrimChar:
3438 load_type = kLoadUnsignedHalfword;
3439 break;
3440 case Primitive::kPrimInt:
3441 case Primitive::kPrimFloat:
3442 case Primitive::kPrimNot:
3443 load_type = kLoadWord;
3444 break;
3445 case Primitive::kPrimLong:
3446 case Primitive::kPrimDouble:
3447 load_type = kLoadDoubleword;
3448 break;
3449 case Primitive::kPrimVoid:
3450 LOG(FATAL) << "Unreachable type " << type;
3451 UNREACHABLE();
3452 }
3453
3454 if (is_volatile && load_type == kLoadDoubleword) {
3455 InvokeRuntimeCallingConvention calling_convention;
3456 __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset);
3457 // Do implicit Null check
3458 __ Lw(ZERO, locations->GetTemp(0).AsRegister<Register>(), 0);
3459 codegen_->RecordPcInfo(instruction, instruction->GetDexPc());
3460 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pA64Load),
3461 instruction,
3462 dex_pc,
3463 nullptr,
3464 IsDirectEntrypoint(kQuickA64Load));
3465 CheckEntrypointTypes<kQuickA64Load, int64_t, volatile const int64_t*>();
3466 if (type == Primitive::kPrimDouble) {
3467 // Need to move to FP regs since FP results are returned in core registers.
3468 __ Mtc1(locations->GetTemp(1).AsRegister<Register>(),
3469 locations->Out().AsFpuRegister<FRegister>());
3470 __ MoveToFpuHigh(locations->GetTemp(2).AsRegister<Register>(),
3471 locations->Out().AsFpuRegister<FRegister>());
3472 }
3473 } else {
3474 if (!Primitive::IsFloatingPointType(type)) {
3475 Register dst;
3476 if (type == Primitive::kPrimLong) {
3477 DCHECK(locations->Out().IsRegisterPair());
3478 dst = locations->Out().AsRegisterPairLow<Register>();
3479 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
3480 if (obj == dst) {
3481 __ LoadFromOffset(kLoadWord, dst_high, obj, offset + kMipsWordSize);
3482 codegen_->MaybeRecordImplicitNullCheck(instruction);
3483 __ LoadFromOffset(kLoadWord, dst, obj, offset);
3484 } else {
3485 __ LoadFromOffset(kLoadWord, dst, obj, offset);
3486 codegen_->MaybeRecordImplicitNullCheck(instruction);
3487 __ LoadFromOffset(kLoadWord, dst_high, obj, offset + kMipsWordSize);
3488 }
3489 } else {
3490 DCHECK(locations->Out().IsRegister());
3491 dst = locations->Out().AsRegister<Register>();
3492 __ LoadFromOffset(load_type, dst, obj, offset);
3493 }
3494 } else {
3495 DCHECK(locations->Out().IsFpuRegister());
3496 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
3497 if (type == Primitive::kPrimFloat) {
3498 __ LoadSFromOffset(dst, obj, offset);
3499 } else {
3500 __ LoadDFromOffset(dst, obj, offset);
3501 }
3502 }
3503 // Longs are handled earlier.
3504 if (type != Primitive::kPrimLong) {
3505 codegen_->MaybeRecordImplicitNullCheck(instruction);
3506 }
3507 }
3508
3509 if (is_volatile) {
3510 GenerateMemoryBarrier(MemBarrierKind::kLoadAny);
3511 }
3512 }
3513
HandleFieldSet(HInstruction * instruction,const FieldInfo & field_info)3514 void LocationsBuilderMIPS::HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info) {
3515 Primitive::Type field_type = field_info.GetFieldType();
3516 bool is_wide = (field_type == Primitive::kPrimLong) || (field_type == Primitive::kPrimDouble);
3517 bool generate_volatile = field_info.IsVolatile() && is_wide;
3518 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(
3519 instruction, generate_volatile ? LocationSummary::kCall : LocationSummary::kNoCall);
3520
3521 locations->SetInAt(0, Location::RequiresRegister());
3522 if (generate_volatile) {
3523 InvokeRuntimeCallingConvention calling_convention;
3524 // need A0 to hold base + offset
3525 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
3526 if (field_type == Primitive::kPrimLong) {
3527 locations->SetInAt(1, Location::RegisterPairLocation(
3528 calling_convention.GetRegisterAt(2), calling_convention.GetRegisterAt(3)));
3529 } else {
3530 locations->SetInAt(1, Location::RequiresFpuRegister());
3531 // Pass FP parameters in core registers.
3532 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(2)));
3533 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(3)));
3534 }
3535 } else {
3536 if (Primitive::IsFloatingPointType(field_type)) {
3537 locations->SetInAt(1, Location::RequiresFpuRegister());
3538 } else {
3539 locations->SetInAt(1, Location::RequiresRegister());
3540 }
3541 }
3542 }
3543
HandleFieldSet(HInstruction * instruction,const FieldInfo & field_info,uint32_t dex_pc)3544 void InstructionCodeGeneratorMIPS::HandleFieldSet(HInstruction* instruction,
3545 const FieldInfo& field_info,
3546 uint32_t dex_pc) {
3547 Primitive::Type type = field_info.GetFieldType();
3548 LocationSummary* locations = instruction->GetLocations();
3549 Register obj = locations->InAt(0).AsRegister<Register>();
3550 StoreOperandType store_type = kStoreByte;
3551 bool is_volatile = field_info.IsVolatile();
3552 uint32_t offset = field_info.GetFieldOffset().Uint32Value();
3553
3554 switch (type) {
3555 case Primitive::kPrimBoolean:
3556 case Primitive::kPrimByte:
3557 store_type = kStoreByte;
3558 break;
3559 case Primitive::kPrimShort:
3560 case Primitive::kPrimChar:
3561 store_type = kStoreHalfword;
3562 break;
3563 case Primitive::kPrimInt:
3564 case Primitive::kPrimFloat:
3565 case Primitive::kPrimNot:
3566 store_type = kStoreWord;
3567 break;
3568 case Primitive::kPrimLong:
3569 case Primitive::kPrimDouble:
3570 store_type = kStoreDoubleword;
3571 break;
3572 case Primitive::kPrimVoid:
3573 LOG(FATAL) << "Unreachable type " << type;
3574 UNREACHABLE();
3575 }
3576
3577 if (is_volatile) {
3578 GenerateMemoryBarrier(MemBarrierKind::kAnyStore);
3579 }
3580
3581 if (is_volatile && store_type == kStoreDoubleword) {
3582 InvokeRuntimeCallingConvention calling_convention;
3583 __ Addiu32(locations->GetTemp(0).AsRegister<Register>(), obj, offset);
3584 // Do implicit Null check.
3585 __ Lw(ZERO, locations->GetTemp(0).AsRegister<Register>(), 0);
3586 codegen_->RecordPcInfo(instruction, instruction->GetDexPc());
3587 if (type == Primitive::kPrimDouble) {
3588 // Pass FP parameters in core registers.
3589 __ Mfc1(locations->GetTemp(1).AsRegister<Register>(),
3590 locations->InAt(1).AsFpuRegister<FRegister>());
3591 __ MoveFromFpuHigh(locations->GetTemp(2).AsRegister<Register>(),
3592 locations->InAt(1).AsFpuRegister<FRegister>());
3593 }
3594 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pA64Store),
3595 instruction,
3596 dex_pc,
3597 nullptr,
3598 IsDirectEntrypoint(kQuickA64Store));
3599 CheckEntrypointTypes<kQuickA64Store, void, volatile int64_t *, int64_t>();
3600 } else {
3601 if (!Primitive::IsFloatingPointType(type)) {
3602 Register src;
3603 if (type == Primitive::kPrimLong) {
3604 DCHECK(locations->InAt(1).IsRegisterPair());
3605 src = locations->InAt(1).AsRegisterPairLow<Register>();
3606 Register src_high = locations->InAt(1).AsRegisterPairHigh<Register>();
3607 __ StoreToOffset(kStoreWord, src, obj, offset);
3608 codegen_->MaybeRecordImplicitNullCheck(instruction);
3609 __ StoreToOffset(kStoreWord, src_high, obj, offset + kMipsWordSize);
3610 } else {
3611 DCHECK(locations->InAt(1).IsRegister());
3612 src = locations->InAt(1).AsRegister<Register>();
3613 __ StoreToOffset(store_type, src, obj, offset);
3614 }
3615 } else {
3616 DCHECK(locations->InAt(1).IsFpuRegister());
3617 FRegister src = locations->InAt(1).AsFpuRegister<FRegister>();
3618 if (type == Primitive::kPrimFloat) {
3619 __ StoreSToOffset(src, obj, offset);
3620 } else {
3621 __ StoreDToOffset(src, obj, offset);
3622 }
3623 }
3624 // Longs are handled earlier.
3625 if (type != Primitive::kPrimLong) {
3626 codegen_->MaybeRecordImplicitNullCheck(instruction);
3627 }
3628 }
3629
3630 // TODO: memory barriers?
3631 if (CodeGenerator::StoreNeedsWriteBarrier(type, instruction->InputAt(1))) {
3632 DCHECK(locations->InAt(1).IsRegister());
3633 Register src = locations->InAt(1).AsRegister<Register>();
3634 codegen_->MarkGCCard(obj, src);
3635 }
3636
3637 if (is_volatile) {
3638 GenerateMemoryBarrier(MemBarrierKind::kAnyAny);
3639 }
3640 }
3641
VisitInstanceFieldGet(HInstanceFieldGet * instruction)3642 void LocationsBuilderMIPS::VisitInstanceFieldGet(HInstanceFieldGet* instruction) {
3643 HandleFieldGet(instruction, instruction->GetFieldInfo());
3644 }
3645
VisitInstanceFieldGet(HInstanceFieldGet * instruction)3646 void InstructionCodeGeneratorMIPS::VisitInstanceFieldGet(HInstanceFieldGet* instruction) {
3647 HandleFieldGet(instruction, instruction->GetFieldInfo(), instruction->GetDexPc());
3648 }
3649
VisitInstanceFieldSet(HInstanceFieldSet * instruction)3650 void LocationsBuilderMIPS::VisitInstanceFieldSet(HInstanceFieldSet* instruction) {
3651 HandleFieldSet(instruction, instruction->GetFieldInfo());
3652 }
3653
VisitInstanceFieldSet(HInstanceFieldSet * instruction)3654 void InstructionCodeGeneratorMIPS::VisitInstanceFieldSet(HInstanceFieldSet* instruction) {
3655 HandleFieldSet(instruction, instruction->GetFieldInfo(), instruction->GetDexPc());
3656 }
3657
VisitInstanceOf(HInstanceOf * instruction)3658 void LocationsBuilderMIPS::VisitInstanceOf(HInstanceOf* instruction) {
3659 LocationSummary::CallKind call_kind =
3660 instruction->IsExactCheck() ? LocationSummary::kNoCall : LocationSummary::kCallOnSlowPath;
3661 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind);
3662 locations->SetInAt(0, Location::RequiresRegister());
3663 locations->SetInAt(1, Location::RequiresRegister());
3664 // The output does overlap inputs.
3665 // Note that TypeCheckSlowPathMIPS uses this register too.
3666 locations->SetOut(Location::RequiresRegister(), Location::kOutputOverlap);
3667 }
3668
VisitInstanceOf(HInstanceOf * instruction)3669 void InstructionCodeGeneratorMIPS::VisitInstanceOf(HInstanceOf* instruction) {
3670 LocationSummary* locations = instruction->GetLocations();
3671 Register obj = locations->InAt(0).AsRegister<Register>();
3672 Register cls = locations->InAt(1).AsRegister<Register>();
3673 Register out = locations->Out().AsRegister<Register>();
3674
3675 MipsLabel done;
3676
3677 // Return 0 if `obj` is null.
3678 // TODO: Avoid this check if we know `obj` is not null.
3679 __ Move(out, ZERO);
3680 __ Beqz(obj, &done);
3681
3682 // Compare the class of `obj` with `cls`.
3683 __ LoadFromOffset(kLoadWord, out, obj, mirror::Object::ClassOffset().Int32Value());
3684 if (instruction->IsExactCheck()) {
3685 // Classes must be equal for the instanceof to succeed.
3686 __ Xor(out, out, cls);
3687 __ Sltiu(out, out, 1);
3688 } else {
3689 // If the classes are not equal, we go into a slow path.
3690 DCHECK(locations->OnlyCallsOnSlowPath());
3691 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) TypeCheckSlowPathMIPS(instruction);
3692 codegen_->AddSlowPath(slow_path);
3693 __ Bne(out, cls, slow_path->GetEntryLabel());
3694 __ LoadConst32(out, 1);
3695 __ Bind(slow_path->GetExitLabel());
3696 }
3697
3698 __ Bind(&done);
3699 }
3700
VisitIntConstant(HIntConstant * constant)3701 void LocationsBuilderMIPS::VisitIntConstant(HIntConstant* constant) {
3702 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(constant);
3703 locations->SetOut(Location::ConstantLocation(constant));
3704 }
3705
VisitIntConstant(HIntConstant * constant ATTRIBUTE_UNUSED)3706 void InstructionCodeGeneratorMIPS::VisitIntConstant(HIntConstant* constant ATTRIBUTE_UNUSED) {
3707 // Will be generated at use site.
3708 }
3709
VisitNullConstant(HNullConstant * constant)3710 void LocationsBuilderMIPS::VisitNullConstant(HNullConstant* constant) {
3711 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(constant);
3712 locations->SetOut(Location::ConstantLocation(constant));
3713 }
3714
VisitNullConstant(HNullConstant * constant ATTRIBUTE_UNUSED)3715 void InstructionCodeGeneratorMIPS::VisitNullConstant(HNullConstant* constant ATTRIBUTE_UNUSED) {
3716 // Will be generated at use site.
3717 }
3718
HandleInvoke(HInvoke * invoke)3719 void LocationsBuilderMIPS::HandleInvoke(HInvoke* invoke) {
3720 InvokeDexCallingConventionVisitorMIPS calling_convention_visitor;
3721 CodeGenerator::CreateCommonInvokeLocationSummary(invoke, &calling_convention_visitor);
3722 }
3723
VisitInvokeInterface(HInvokeInterface * invoke)3724 void LocationsBuilderMIPS::VisitInvokeInterface(HInvokeInterface* invoke) {
3725 HandleInvoke(invoke);
3726 // The register T0 is required to be used for the hidden argument in
3727 // art_quick_imt_conflict_trampoline, so add the hidden argument.
3728 invoke->GetLocations()->AddTemp(Location::RegisterLocation(T0));
3729 }
3730
VisitInvokeInterface(HInvokeInterface * invoke)3731 void InstructionCodeGeneratorMIPS::VisitInvokeInterface(HInvokeInterface* invoke) {
3732 // TODO: b/18116999, our IMTs can miss an IncompatibleClassChangeError.
3733 Register temp = invoke->GetLocations()->GetTemp(0).AsRegister<Register>();
3734 Location receiver = invoke->GetLocations()->InAt(0);
3735 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value();
3736 Offset entry_point = ArtMethod::EntryPointFromQuickCompiledCodeOffset(kMipsWordSize);
3737
3738 // Set the hidden argument.
3739 __ LoadConst32(invoke->GetLocations()->GetTemp(1).AsRegister<Register>(),
3740 invoke->GetDexMethodIndex());
3741
3742 // temp = object->GetClass();
3743 if (receiver.IsStackSlot()) {
3744 __ LoadFromOffset(kLoadWord, temp, SP, receiver.GetStackIndex());
3745 __ LoadFromOffset(kLoadWord, temp, temp, class_offset);
3746 } else {
3747 __ LoadFromOffset(kLoadWord, temp, receiver.AsRegister<Register>(), class_offset);
3748 }
3749 codegen_->MaybeRecordImplicitNullCheck(invoke);
3750 __ LoadFromOffset(kLoadWord, temp, temp,
3751 mirror::Class::ImtPtrOffset(kMipsPointerSize).Uint32Value());
3752 uint32_t method_offset = static_cast<uint32_t>(ImTable::OffsetOfElement(
3753 invoke->GetImtIndex() % ImTable::kSize, kMipsPointerSize));
3754 // temp = temp->GetImtEntryAt(method_offset);
3755 __ LoadFromOffset(kLoadWord, temp, temp, method_offset);
3756 // T9 = temp->GetEntryPoint();
3757 __ LoadFromOffset(kLoadWord, T9, temp, entry_point.Int32Value());
3758 // T9();
3759 __ Jalr(T9);
3760 __ Nop();
3761 DCHECK(!codegen_->IsLeafMethod());
3762 codegen_->RecordPcInfo(invoke, invoke->GetDexPc());
3763 }
3764
VisitInvokeVirtual(HInvokeVirtual * invoke)3765 void LocationsBuilderMIPS::VisitInvokeVirtual(HInvokeVirtual* invoke) {
3766 IntrinsicLocationsBuilderMIPS intrinsic(codegen_);
3767 if (intrinsic.TryDispatch(invoke)) {
3768 return;
3769 }
3770
3771 HandleInvoke(invoke);
3772 }
3773
VisitInvokeStaticOrDirect(HInvokeStaticOrDirect * invoke)3774 void LocationsBuilderMIPS::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) {
3775 // Explicit clinit checks triggered by static invokes must have been pruned by
3776 // art::PrepareForRegisterAllocation.
3777 DCHECK(!invoke->IsStaticWithExplicitClinitCheck());
3778
3779 IntrinsicLocationsBuilderMIPS intrinsic(codegen_);
3780 if (intrinsic.TryDispatch(invoke)) {
3781 return;
3782 }
3783
3784 HandleInvoke(invoke);
3785 }
3786
TryGenerateIntrinsicCode(HInvoke * invoke,CodeGeneratorMIPS * codegen)3787 static bool TryGenerateIntrinsicCode(HInvoke* invoke, CodeGeneratorMIPS* codegen) {
3788 if (invoke->GetLocations()->Intrinsified()) {
3789 IntrinsicCodeGeneratorMIPS intrinsic(codegen);
3790 intrinsic.Dispatch(invoke);
3791 return true;
3792 }
3793 return false;
3794 }
3795
GetSupportedLoadStringKind(HLoadString::LoadKind desired_string_load_kind ATTRIBUTE_UNUSED)3796 HLoadString::LoadKind CodeGeneratorMIPS::GetSupportedLoadStringKind(
3797 HLoadString::LoadKind desired_string_load_kind ATTRIBUTE_UNUSED) {
3798 // TODO: Implement other kinds.
3799 return HLoadString::LoadKind::kDexCacheViaMethod;
3800 }
3801
GetSupportedInvokeStaticOrDirectDispatch(const HInvokeStaticOrDirect::DispatchInfo & desired_dispatch_info,MethodReference target_method ATTRIBUTE_UNUSED)3802 HInvokeStaticOrDirect::DispatchInfo CodeGeneratorMIPS::GetSupportedInvokeStaticOrDirectDispatch(
3803 const HInvokeStaticOrDirect::DispatchInfo& desired_dispatch_info,
3804 MethodReference target_method ATTRIBUTE_UNUSED) {
3805 switch (desired_dispatch_info.method_load_kind) {
3806 case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddressWithFixup:
3807 case HInvokeStaticOrDirect::MethodLoadKind::kDexCachePcRelative:
3808 // TODO: Implement these types. For the moment, we fall back to kDexCacheViaMethod.
3809 return HInvokeStaticOrDirect::DispatchInfo {
3810 HInvokeStaticOrDirect::MethodLoadKind::kDexCacheViaMethod,
3811 HInvokeStaticOrDirect::CodePtrLocation::kCallArtMethod,
3812 0u,
3813 0u
3814 };
3815 default:
3816 break;
3817 }
3818 switch (desired_dispatch_info.code_ptr_location) {
3819 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirectWithFixup:
3820 case HInvokeStaticOrDirect::CodePtrLocation::kCallPCRelative:
3821 // TODO: Implement these types. For the moment, we fall back to kCallArtMethod.
3822 return HInvokeStaticOrDirect::DispatchInfo {
3823 desired_dispatch_info.method_load_kind,
3824 HInvokeStaticOrDirect::CodePtrLocation::kCallArtMethod,
3825 desired_dispatch_info.method_load_data,
3826 0u
3827 };
3828 default:
3829 return desired_dispatch_info;
3830 }
3831 }
3832
GenerateStaticOrDirectCall(HInvokeStaticOrDirect * invoke,Location temp)3833 void CodeGeneratorMIPS::GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Location temp) {
3834 // All registers are assumed to be correctly set up per the calling convention.
3835
3836 Location callee_method = temp; // For all kinds except kRecursive, callee will be in temp.
3837 switch (invoke->GetMethodLoadKind()) {
3838 case HInvokeStaticOrDirect::MethodLoadKind::kStringInit:
3839 // temp = thread->string_init_entrypoint
3840 __ LoadFromOffset(kLoadWord,
3841 temp.AsRegister<Register>(),
3842 TR,
3843 invoke->GetStringInitOffset());
3844 break;
3845 case HInvokeStaticOrDirect::MethodLoadKind::kRecursive:
3846 callee_method = invoke->GetLocations()->InAt(invoke->GetSpecialInputIndex());
3847 break;
3848 case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddress:
3849 __ LoadConst32(temp.AsRegister<Register>(), invoke->GetMethodAddress());
3850 break;
3851 case HInvokeStaticOrDirect::MethodLoadKind::kDirectAddressWithFixup:
3852 case HInvokeStaticOrDirect::MethodLoadKind::kDexCachePcRelative:
3853 // TODO: Implement these types.
3854 // Currently filtered out by GetSupportedInvokeStaticOrDirectDispatch().
3855 LOG(FATAL) << "Unsupported";
3856 UNREACHABLE();
3857 case HInvokeStaticOrDirect::MethodLoadKind::kDexCacheViaMethod: {
3858 Location current_method = invoke->GetLocations()->InAt(invoke->GetSpecialInputIndex());
3859 Register reg = temp.AsRegister<Register>();
3860 Register method_reg;
3861 if (current_method.IsRegister()) {
3862 method_reg = current_method.AsRegister<Register>();
3863 } else {
3864 // TODO: use the appropriate DCHECK() here if possible.
3865 // DCHECK(invoke->GetLocations()->Intrinsified());
3866 DCHECK(!current_method.IsValid());
3867 method_reg = reg;
3868 __ Lw(reg, SP, kCurrentMethodStackOffset);
3869 }
3870
3871 // temp = temp->dex_cache_resolved_methods_;
3872 __ LoadFromOffset(kLoadWord,
3873 reg,
3874 method_reg,
3875 ArtMethod::DexCacheResolvedMethodsOffset(kMipsPointerSize).Int32Value());
3876 // temp = temp[index_in_cache];
3877 // Note: Don't use invoke->GetTargetMethod() as it may point to a different dex file.
3878 uint32_t index_in_cache = invoke->GetDexMethodIndex();
3879 __ LoadFromOffset(kLoadWord,
3880 reg,
3881 reg,
3882 CodeGenerator::GetCachePointerOffset(index_in_cache));
3883 break;
3884 }
3885 }
3886
3887 switch (invoke->GetCodePtrLocation()) {
3888 case HInvokeStaticOrDirect::CodePtrLocation::kCallSelf:
3889 __ Jalr(&frame_entry_label_, T9);
3890 break;
3891 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirect:
3892 // LR = invoke->GetDirectCodePtr();
3893 __ LoadConst32(T9, invoke->GetDirectCodePtr());
3894 // LR()
3895 __ Jalr(T9);
3896 __ Nop();
3897 break;
3898 case HInvokeStaticOrDirect::CodePtrLocation::kCallDirectWithFixup:
3899 case HInvokeStaticOrDirect::CodePtrLocation::kCallPCRelative:
3900 // TODO: Implement these types.
3901 // Currently filtered out by GetSupportedInvokeStaticOrDirectDispatch().
3902 LOG(FATAL) << "Unsupported";
3903 UNREACHABLE();
3904 case HInvokeStaticOrDirect::CodePtrLocation::kCallArtMethod:
3905 // T9 = callee_method->entry_point_from_quick_compiled_code_;
3906 __ LoadFromOffset(kLoadWord,
3907 T9,
3908 callee_method.AsRegister<Register>(),
3909 ArtMethod::EntryPointFromQuickCompiledCodeOffset(
3910 kMipsWordSize).Int32Value());
3911 // T9()
3912 __ Jalr(T9);
3913 __ Nop();
3914 break;
3915 }
3916 DCHECK(!IsLeafMethod());
3917 }
3918
VisitInvokeStaticOrDirect(HInvokeStaticOrDirect * invoke)3919 void InstructionCodeGeneratorMIPS::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) {
3920 // Explicit clinit checks triggered by static invokes must have been pruned by
3921 // art::PrepareForRegisterAllocation.
3922 DCHECK(!invoke->IsStaticWithExplicitClinitCheck());
3923
3924 if (TryGenerateIntrinsicCode(invoke, codegen_)) {
3925 return;
3926 }
3927
3928 LocationSummary* locations = invoke->GetLocations();
3929 codegen_->GenerateStaticOrDirectCall(invoke,
3930 locations->HasTemps()
3931 ? locations->GetTemp(0)
3932 : Location::NoLocation());
3933 codegen_->RecordPcInfo(invoke, invoke->GetDexPc());
3934 }
3935
GenerateVirtualCall(HInvokeVirtual * invoke,Location temp_location)3936 void CodeGeneratorMIPS::GenerateVirtualCall(HInvokeVirtual* invoke, Location temp_location) {
3937 LocationSummary* locations = invoke->GetLocations();
3938 Location receiver = locations->InAt(0);
3939 Register temp = temp_location.AsRegister<Register>();
3940 size_t method_offset = mirror::Class::EmbeddedVTableEntryOffset(
3941 invoke->GetVTableIndex(), kMipsPointerSize).SizeValue();
3942 uint32_t class_offset = mirror::Object::ClassOffset().Int32Value();
3943 Offset entry_point = ArtMethod::EntryPointFromQuickCompiledCodeOffset(kMipsWordSize);
3944
3945 // temp = object->GetClass();
3946 DCHECK(receiver.IsRegister());
3947 __ LoadFromOffset(kLoadWord, temp, receiver.AsRegister<Register>(), class_offset);
3948 MaybeRecordImplicitNullCheck(invoke);
3949 // temp = temp->GetMethodAt(method_offset);
3950 __ LoadFromOffset(kLoadWord, temp, temp, method_offset);
3951 // T9 = temp->GetEntryPoint();
3952 __ LoadFromOffset(kLoadWord, T9, temp, entry_point.Int32Value());
3953 // T9();
3954 __ Jalr(T9);
3955 __ Nop();
3956 }
3957
VisitInvokeVirtual(HInvokeVirtual * invoke)3958 void InstructionCodeGeneratorMIPS::VisitInvokeVirtual(HInvokeVirtual* invoke) {
3959 if (TryGenerateIntrinsicCode(invoke, codegen_)) {
3960 return;
3961 }
3962
3963 codegen_->GenerateVirtualCall(invoke, invoke->GetLocations()->GetTemp(0));
3964 DCHECK(!codegen_->IsLeafMethod());
3965 codegen_->RecordPcInfo(invoke, invoke->GetDexPc());
3966 }
3967
VisitLoadClass(HLoadClass * cls)3968 void LocationsBuilderMIPS::VisitLoadClass(HLoadClass* cls) {
3969 InvokeRuntimeCallingConvention calling_convention;
3970 CodeGenerator::CreateLoadClassLocationSummary(
3971 cls,
3972 Location::RegisterLocation(calling_convention.GetRegisterAt(0)),
3973 Location::RegisterLocation(V0));
3974 }
3975
VisitLoadClass(HLoadClass * cls)3976 void InstructionCodeGeneratorMIPS::VisitLoadClass(HLoadClass* cls) {
3977 LocationSummary* locations = cls->GetLocations();
3978 if (cls->NeedsAccessCheck()) {
3979 codegen_->MoveConstant(locations->GetTemp(0), cls->GetTypeIndex());
3980 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pInitializeTypeAndVerifyAccess),
3981 cls,
3982 cls->GetDexPc(),
3983 nullptr,
3984 IsDirectEntrypoint(kQuickInitializeTypeAndVerifyAccess));
3985 CheckEntrypointTypes<kQuickInitializeTypeAndVerifyAccess, void*, uint32_t>();
3986 return;
3987 }
3988
3989 Register out = locations->Out().AsRegister<Register>();
3990 Register current_method = locations->InAt(0).AsRegister<Register>();
3991 if (cls->IsReferrersClass()) {
3992 DCHECK(!cls->CanCallRuntime());
3993 DCHECK(!cls->MustGenerateClinitCheck());
3994 __ LoadFromOffset(kLoadWord, out, current_method,
3995 ArtMethod::DeclaringClassOffset().Int32Value());
3996 } else {
3997 __ LoadFromOffset(kLoadWord, out, current_method,
3998 ArtMethod::DexCacheResolvedTypesOffset(kMipsPointerSize).Int32Value());
3999 __ LoadFromOffset(kLoadWord, out, out, CodeGenerator::GetCacheOffset(cls->GetTypeIndex()));
4000
4001 if (!cls->IsInDexCache() || cls->MustGenerateClinitCheck()) {
4002 DCHECK(cls->CanCallRuntime());
4003 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) LoadClassSlowPathMIPS(
4004 cls,
4005 cls,
4006 cls->GetDexPc(),
4007 cls->MustGenerateClinitCheck());
4008 codegen_->AddSlowPath(slow_path);
4009 if (!cls->IsInDexCache()) {
4010 __ Beqz(out, slow_path->GetEntryLabel());
4011 }
4012 if (cls->MustGenerateClinitCheck()) {
4013 GenerateClassInitializationCheck(slow_path, out);
4014 } else {
4015 __ Bind(slow_path->GetExitLabel());
4016 }
4017 }
4018 }
4019 }
4020
GetExceptionTlsOffset()4021 static int32_t GetExceptionTlsOffset() {
4022 return Thread::ExceptionOffset<kMipsWordSize>().Int32Value();
4023 }
4024
VisitLoadException(HLoadException * load)4025 void LocationsBuilderMIPS::VisitLoadException(HLoadException* load) {
4026 LocationSummary* locations =
4027 new (GetGraph()->GetArena()) LocationSummary(load, LocationSummary::kNoCall);
4028 locations->SetOut(Location::RequiresRegister());
4029 }
4030
VisitLoadException(HLoadException * load)4031 void InstructionCodeGeneratorMIPS::VisitLoadException(HLoadException* load) {
4032 Register out = load->GetLocations()->Out().AsRegister<Register>();
4033 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset());
4034 }
4035
VisitClearException(HClearException * clear)4036 void LocationsBuilderMIPS::VisitClearException(HClearException* clear) {
4037 new (GetGraph()->GetArena()) LocationSummary(clear, LocationSummary::kNoCall);
4038 }
4039
VisitClearException(HClearException * clear ATTRIBUTE_UNUSED)4040 void InstructionCodeGeneratorMIPS::VisitClearException(HClearException* clear ATTRIBUTE_UNUSED) {
4041 __ StoreToOffset(kStoreWord, ZERO, TR, GetExceptionTlsOffset());
4042 }
4043
VisitLoadString(HLoadString * load)4044 void LocationsBuilderMIPS::VisitLoadString(HLoadString* load) {
4045 LocationSummary::CallKind call_kind = load->NeedsEnvironment()
4046 ? LocationSummary::kCallOnSlowPath
4047 : LocationSummary::kNoCall;
4048 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(load, call_kind);
4049 locations->SetInAt(0, Location::RequiresRegister());
4050 locations->SetOut(Location::RequiresRegister());
4051 }
4052
VisitLoadString(HLoadString * load)4053 void InstructionCodeGeneratorMIPS::VisitLoadString(HLoadString* load) {
4054 LocationSummary* locations = load->GetLocations();
4055 Register out = locations->Out().AsRegister<Register>();
4056 Register current_method = locations->InAt(0).AsRegister<Register>();
4057 __ LoadFromOffset(kLoadWord, out, current_method, ArtMethod::DeclaringClassOffset().Int32Value());
4058 __ LoadFromOffset(kLoadWord, out, out, mirror::Class::DexCacheStringsOffset().Int32Value());
4059 __ LoadFromOffset(kLoadWord, out, out, CodeGenerator::GetCacheOffset(load->GetStringIndex()));
4060
4061 if (!load->IsInDexCache()) {
4062 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) LoadStringSlowPathMIPS(load);
4063 codegen_->AddSlowPath(slow_path);
4064 __ Beqz(out, slow_path->GetEntryLabel());
4065 __ Bind(slow_path->GetExitLabel());
4066 }
4067 }
4068
VisitLongConstant(HLongConstant * constant)4069 void LocationsBuilderMIPS::VisitLongConstant(HLongConstant* constant) {
4070 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(constant);
4071 locations->SetOut(Location::ConstantLocation(constant));
4072 }
4073
VisitLongConstant(HLongConstant * constant ATTRIBUTE_UNUSED)4074 void InstructionCodeGeneratorMIPS::VisitLongConstant(HLongConstant* constant ATTRIBUTE_UNUSED) {
4075 // Will be generated at use site.
4076 }
4077
VisitMonitorOperation(HMonitorOperation * instruction)4078 void LocationsBuilderMIPS::VisitMonitorOperation(HMonitorOperation* instruction) {
4079 LocationSummary* locations =
4080 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCall);
4081 InvokeRuntimeCallingConvention calling_convention;
4082 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
4083 }
4084
VisitMonitorOperation(HMonitorOperation * instruction)4085 void InstructionCodeGeneratorMIPS::VisitMonitorOperation(HMonitorOperation* instruction) {
4086 if (instruction->IsEnter()) {
4087 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pLockObject),
4088 instruction,
4089 instruction->GetDexPc(),
4090 nullptr,
4091 IsDirectEntrypoint(kQuickLockObject));
4092 CheckEntrypointTypes<kQuickLockObject, void, mirror::Object*>();
4093 } else {
4094 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pUnlockObject),
4095 instruction,
4096 instruction->GetDexPc(),
4097 nullptr,
4098 IsDirectEntrypoint(kQuickUnlockObject));
4099 }
4100 CheckEntrypointTypes<kQuickUnlockObject, void, mirror::Object*>();
4101 }
4102
VisitMul(HMul * mul)4103 void LocationsBuilderMIPS::VisitMul(HMul* mul) {
4104 LocationSummary* locations =
4105 new (GetGraph()->GetArena()) LocationSummary(mul, LocationSummary::kNoCall);
4106 switch (mul->GetResultType()) {
4107 case Primitive::kPrimInt:
4108 case Primitive::kPrimLong:
4109 locations->SetInAt(0, Location::RequiresRegister());
4110 locations->SetInAt(1, Location::RequiresRegister());
4111 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4112 break;
4113
4114 case Primitive::kPrimFloat:
4115 case Primitive::kPrimDouble:
4116 locations->SetInAt(0, Location::RequiresFpuRegister());
4117 locations->SetInAt(1, Location::RequiresFpuRegister());
4118 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
4119 break;
4120
4121 default:
4122 LOG(FATAL) << "Unexpected mul type " << mul->GetResultType();
4123 }
4124 }
4125
VisitMul(HMul * instruction)4126 void InstructionCodeGeneratorMIPS::VisitMul(HMul* instruction) {
4127 Primitive::Type type = instruction->GetType();
4128 LocationSummary* locations = instruction->GetLocations();
4129 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
4130
4131 switch (type) {
4132 case Primitive::kPrimInt: {
4133 Register dst = locations->Out().AsRegister<Register>();
4134 Register lhs = locations->InAt(0).AsRegister<Register>();
4135 Register rhs = locations->InAt(1).AsRegister<Register>();
4136
4137 if (isR6) {
4138 __ MulR6(dst, lhs, rhs);
4139 } else {
4140 __ MulR2(dst, lhs, rhs);
4141 }
4142 break;
4143 }
4144 case Primitive::kPrimLong: {
4145 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4146 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4147 Register lhs_high = locations->InAt(0).AsRegisterPairHigh<Register>();
4148 Register lhs_low = locations->InAt(0).AsRegisterPairLow<Register>();
4149 Register rhs_high = locations->InAt(1).AsRegisterPairHigh<Register>();
4150 Register rhs_low = locations->InAt(1).AsRegisterPairLow<Register>();
4151
4152 // Extra checks to protect caused by the existance of A1_A2.
4153 // The algorithm is wrong if dst_high is either lhs_lo or rhs_lo:
4154 // (e.g. lhs=a0_a1, rhs=a2_a3 and dst=a1_a2).
4155 DCHECK_NE(dst_high, lhs_low);
4156 DCHECK_NE(dst_high, rhs_low);
4157
4158 // A_B * C_D
4159 // dst_hi: [ low(A*D) + low(B*C) + hi(B*D) ]
4160 // dst_lo: [ low(B*D) ]
4161 // Note: R2 and R6 MUL produce the low 32 bit of the multiplication result.
4162
4163 if (isR6) {
4164 __ MulR6(TMP, lhs_high, rhs_low);
4165 __ MulR6(dst_high, lhs_low, rhs_high);
4166 __ Addu(dst_high, dst_high, TMP);
4167 __ MuhuR6(TMP, lhs_low, rhs_low);
4168 __ Addu(dst_high, dst_high, TMP);
4169 __ MulR6(dst_low, lhs_low, rhs_low);
4170 } else {
4171 __ MulR2(TMP, lhs_high, rhs_low);
4172 __ MulR2(dst_high, lhs_low, rhs_high);
4173 __ Addu(dst_high, dst_high, TMP);
4174 __ MultuR2(lhs_low, rhs_low);
4175 __ Mfhi(TMP);
4176 __ Addu(dst_high, dst_high, TMP);
4177 __ Mflo(dst_low);
4178 }
4179 break;
4180 }
4181 case Primitive::kPrimFloat:
4182 case Primitive::kPrimDouble: {
4183 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4184 FRegister lhs = locations->InAt(0).AsFpuRegister<FRegister>();
4185 FRegister rhs = locations->InAt(1).AsFpuRegister<FRegister>();
4186 if (type == Primitive::kPrimFloat) {
4187 __ MulS(dst, lhs, rhs);
4188 } else {
4189 __ MulD(dst, lhs, rhs);
4190 }
4191 break;
4192 }
4193 default:
4194 LOG(FATAL) << "Unexpected mul type " << type;
4195 }
4196 }
4197
VisitNeg(HNeg * neg)4198 void LocationsBuilderMIPS::VisitNeg(HNeg* neg) {
4199 LocationSummary* locations =
4200 new (GetGraph()->GetArena()) LocationSummary(neg, LocationSummary::kNoCall);
4201 switch (neg->GetResultType()) {
4202 case Primitive::kPrimInt:
4203 case Primitive::kPrimLong:
4204 locations->SetInAt(0, Location::RequiresRegister());
4205 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4206 break;
4207
4208 case Primitive::kPrimFloat:
4209 case Primitive::kPrimDouble:
4210 locations->SetInAt(0, Location::RequiresFpuRegister());
4211 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
4212 break;
4213
4214 default:
4215 LOG(FATAL) << "Unexpected neg type " << neg->GetResultType();
4216 }
4217 }
4218
VisitNeg(HNeg * instruction)4219 void InstructionCodeGeneratorMIPS::VisitNeg(HNeg* instruction) {
4220 Primitive::Type type = instruction->GetType();
4221 LocationSummary* locations = instruction->GetLocations();
4222
4223 switch (type) {
4224 case Primitive::kPrimInt: {
4225 Register dst = locations->Out().AsRegister<Register>();
4226 Register src = locations->InAt(0).AsRegister<Register>();
4227 __ Subu(dst, ZERO, src);
4228 break;
4229 }
4230 case Primitive::kPrimLong: {
4231 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4232 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4233 Register src_high = locations->InAt(0).AsRegisterPairHigh<Register>();
4234 Register src_low = locations->InAt(0).AsRegisterPairLow<Register>();
4235 __ Subu(dst_low, ZERO, src_low);
4236 __ Sltu(TMP, ZERO, dst_low);
4237 __ Subu(dst_high, ZERO, src_high);
4238 __ Subu(dst_high, dst_high, TMP);
4239 break;
4240 }
4241 case Primitive::kPrimFloat:
4242 case Primitive::kPrimDouble: {
4243 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4244 FRegister src = locations->InAt(0).AsFpuRegister<FRegister>();
4245 if (type == Primitive::kPrimFloat) {
4246 __ NegS(dst, src);
4247 } else {
4248 __ NegD(dst, src);
4249 }
4250 break;
4251 }
4252 default:
4253 LOG(FATAL) << "Unexpected neg type " << type;
4254 }
4255 }
4256
VisitNewArray(HNewArray * instruction)4257 void LocationsBuilderMIPS::VisitNewArray(HNewArray* instruction) {
4258 LocationSummary* locations =
4259 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCall);
4260 InvokeRuntimeCallingConvention calling_convention;
4261 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
4262 locations->AddTemp(Location::RegisterLocation(calling_convention.GetRegisterAt(2)));
4263 locations->SetOut(calling_convention.GetReturnLocation(Primitive::kPrimNot));
4264 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(1)));
4265 }
4266
VisitNewArray(HNewArray * instruction)4267 void InstructionCodeGeneratorMIPS::VisitNewArray(HNewArray* instruction) {
4268 InvokeRuntimeCallingConvention calling_convention;
4269 Register current_method_register = calling_convention.GetRegisterAt(2);
4270 __ Lw(current_method_register, SP, kCurrentMethodStackOffset);
4271 // Move an uint16_t value to a register.
4272 __ LoadConst32(calling_convention.GetRegisterAt(0), instruction->GetTypeIndex());
4273 codegen_->InvokeRuntime(
4274 GetThreadOffset<kMipsWordSize>(instruction->GetEntrypoint()).Int32Value(),
4275 instruction,
4276 instruction->GetDexPc(),
4277 nullptr,
4278 IsDirectEntrypoint(kQuickAllocArrayWithAccessCheck));
4279 CheckEntrypointTypes<kQuickAllocArrayWithAccessCheck,
4280 void*, uint32_t, int32_t, ArtMethod*>();
4281 }
4282
VisitNewInstance(HNewInstance * instruction)4283 void LocationsBuilderMIPS::VisitNewInstance(HNewInstance* instruction) {
4284 LocationSummary* locations =
4285 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCall);
4286 InvokeRuntimeCallingConvention calling_convention;
4287 if (instruction->IsStringAlloc()) {
4288 locations->AddTemp(Location::RegisterLocation(kMethodRegisterArgument));
4289 } else {
4290 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
4291 locations->SetInAt(1, Location::RegisterLocation(calling_convention.GetRegisterAt(1)));
4292 }
4293 locations->SetOut(calling_convention.GetReturnLocation(Primitive::kPrimNot));
4294 }
4295
VisitNewInstance(HNewInstance * instruction)4296 void InstructionCodeGeneratorMIPS::VisitNewInstance(HNewInstance* instruction) {
4297 if (instruction->IsStringAlloc()) {
4298 // String is allocated through StringFactory. Call NewEmptyString entry point.
4299 Register temp = instruction->GetLocations()->GetTemp(0).AsRegister<Register>();
4300 MemberOffset code_offset = ArtMethod::EntryPointFromQuickCompiledCodeOffset(kMipsWordSize);
4301 __ LoadFromOffset(kLoadWord, temp, TR, QUICK_ENTRY_POINT(pNewEmptyString));
4302 __ LoadFromOffset(kLoadWord, T9, temp, code_offset.Int32Value());
4303 __ Jalr(T9);
4304 __ Nop();
4305 codegen_->RecordPcInfo(instruction, instruction->GetDexPc());
4306 } else {
4307 codegen_->InvokeRuntime(
4308 GetThreadOffset<kMipsWordSize>(instruction->GetEntrypoint()).Int32Value(),
4309 instruction,
4310 instruction->GetDexPc(),
4311 nullptr,
4312 IsDirectEntrypoint(kQuickAllocObjectWithAccessCheck));
4313 CheckEntrypointTypes<kQuickAllocObjectWithAccessCheck, void*, uint32_t, ArtMethod*>();
4314 }
4315 }
4316
VisitNot(HNot * instruction)4317 void LocationsBuilderMIPS::VisitNot(HNot* instruction) {
4318 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
4319 locations->SetInAt(0, Location::RequiresRegister());
4320 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4321 }
4322
VisitNot(HNot * instruction)4323 void InstructionCodeGeneratorMIPS::VisitNot(HNot* instruction) {
4324 Primitive::Type type = instruction->GetType();
4325 LocationSummary* locations = instruction->GetLocations();
4326
4327 switch (type) {
4328 case Primitive::kPrimInt: {
4329 Register dst = locations->Out().AsRegister<Register>();
4330 Register src = locations->InAt(0).AsRegister<Register>();
4331 __ Nor(dst, src, ZERO);
4332 break;
4333 }
4334
4335 case Primitive::kPrimLong: {
4336 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4337 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4338 Register src_high = locations->InAt(0).AsRegisterPairHigh<Register>();
4339 Register src_low = locations->InAt(0).AsRegisterPairLow<Register>();
4340 __ Nor(dst_high, src_high, ZERO);
4341 __ Nor(dst_low, src_low, ZERO);
4342 break;
4343 }
4344
4345 default:
4346 LOG(FATAL) << "Unexpected type for not operation " << instruction->GetResultType();
4347 }
4348 }
4349
VisitBooleanNot(HBooleanNot * instruction)4350 void LocationsBuilderMIPS::VisitBooleanNot(HBooleanNot* instruction) {
4351 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
4352 locations->SetInAt(0, Location::RequiresRegister());
4353 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4354 }
4355
VisitBooleanNot(HBooleanNot * instruction)4356 void InstructionCodeGeneratorMIPS::VisitBooleanNot(HBooleanNot* instruction) {
4357 LocationSummary* locations = instruction->GetLocations();
4358 __ Xori(locations->Out().AsRegister<Register>(),
4359 locations->InAt(0).AsRegister<Register>(),
4360 1);
4361 }
4362
VisitNullCheck(HNullCheck * instruction)4363 void LocationsBuilderMIPS::VisitNullCheck(HNullCheck* instruction) {
4364 LocationSummary::CallKind call_kind = instruction->CanThrowIntoCatchBlock()
4365 ? LocationSummary::kCallOnSlowPath
4366 : LocationSummary::kNoCall;
4367 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction, call_kind);
4368 locations->SetInAt(0, Location::RequiresRegister());
4369 if (instruction->HasUses()) {
4370 locations->SetOut(Location::SameAsFirstInput());
4371 }
4372 }
4373
GenerateImplicitNullCheck(HNullCheck * instruction)4374 void CodeGeneratorMIPS::GenerateImplicitNullCheck(HNullCheck* instruction) {
4375 if (CanMoveNullCheckToUser(instruction)) {
4376 return;
4377 }
4378 Location obj = instruction->GetLocations()->InAt(0);
4379
4380 __ Lw(ZERO, obj.AsRegister<Register>(), 0);
4381 RecordPcInfo(instruction, instruction->GetDexPc());
4382 }
4383
GenerateExplicitNullCheck(HNullCheck * instruction)4384 void CodeGeneratorMIPS::GenerateExplicitNullCheck(HNullCheck* instruction) {
4385 SlowPathCodeMIPS* slow_path = new (GetGraph()->GetArena()) NullCheckSlowPathMIPS(instruction);
4386 AddSlowPath(slow_path);
4387
4388 Location obj = instruction->GetLocations()->InAt(0);
4389
4390 __ Beqz(obj.AsRegister<Register>(), slow_path->GetEntryLabel());
4391 }
4392
VisitNullCheck(HNullCheck * instruction)4393 void InstructionCodeGeneratorMIPS::VisitNullCheck(HNullCheck* instruction) {
4394 codegen_->GenerateNullCheck(instruction);
4395 }
4396
VisitOr(HOr * instruction)4397 void LocationsBuilderMIPS::VisitOr(HOr* instruction) {
4398 HandleBinaryOp(instruction);
4399 }
4400
VisitOr(HOr * instruction)4401 void InstructionCodeGeneratorMIPS::VisitOr(HOr* instruction) {
4402 HandleBinaryOp(instruction);
4403 }
4404
VisitParallelMove(HParallelMove * instruction ATTRIBUTE_UNUSED)4405 void LocationsBuilderMIPS::VisitParallelMove(HParallelMove* instruction ATTRIBUTE_UNUSED) {
4406 LOG(FATAL) << "Unreachable";
4407 }
4408
VisitParallelMove(HParallelMove * instruction)4409 void InstructionCodeGeneratorMIPS::VisitParallelMove(HParallelMove* instruction) {
4410 codegen_->GetMoveResolver()->EmitNativeCode(instruction);
4411 }
4412
VisitParameterValue(HParameterValue * instruction)4413 void LocationsBuilderMIPS::VisitParameterValue(HParameterValue* instruction) {
4414 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
4415 Location location = parameter_visitor_.GetNextLocation(instruction->GetType());
4416 if (location.IsStackSlot()) {
4417 location = Location::StackSlot(location.GetStackIndex() + codegen_->GetFrameSize());
4418 } else if (location.IsDoubleStackSlot()) {
4419 location = Location::DoubleStackSlot(location.GetStackIndex() + codegen_->GetFrameSize());
4420 }
4421 locations->SetOut(location);
4422 }
4423
VisitParameterValue(HParameterValue * instruction ATTRIBUTE_UNUSED)4424 void InstructionCodeGeneratorMIPS::VisitParameterValue(HParameterValue* instruction
4425 ATTRIBUTE_UNUSED) {
4426 // Nothing to do, the parameter is already at its location.
4427 }
4428
VisitCurrentMethod(HCurrentMethod * instruction)4429 void LocationsBuilderMIPS::VisitCurrentMethod(HCurrentMethod* instruction) {
4430 LocationSummary* locations =
4431 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall);
4432 locations->SetOut(Location::RegisterLocation(kMethodRegisterArgument));
4433 }
4434
VisitCurrentMethod(HCurrentMethod * instruction ATTRIBUTE_UNUSED)4435 void InstructionCodeGeneratorMIPS::VisitCurrentMethod(HCurrentMethod* instruction
4436 ATTRIBUTE_UNUSED) {
4437 // Nothing to do, the method is already at its location.
4438 }
4439
VisitPhi(HPhi * instruction)4440 void LocationsBuilderMIPS::VisitPhi(HPhi* instruction) {
4441 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(instruction);
4442 for (size_t i = 0, e = instruction->InputCount(); i < e; ++i) {
4443 locations->SetInAt(i, Location::Any());
4444 }
4445 locations->SetOut(Location::Any());
4446 }
4447
VisitPhi(HPhi * instruction ATTRIBUTE_UNUSED)4448 void InstructionCodeGeneratorMIPS::VisitPhi(HPhi* instruction ATTRIBUTE_UNUSED) {
4449 LOG(FATAL) << "Unreachable";
4450 }
4451
VisitRem(HRem * rem)4452 void LocationsBuilderMIPS::VisitRem(HRem* rem) {
4453 Primitive::Type type = rem->GetResultType();
4454 LocationSummary::CallKind call_kind =
4455 (type == Primitive::kPrimInt) ? LocationSummary::kNoCall : LocationSummary::kCall;
4456 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(rem, call_kind);
4457
4458 switch (type) {
4459 case Primitive::kPrimInt:
4460 locations->SetInAt(0, Location::RequiresRegister());
4461 locations->SetInAt(1, Location::RegisterOrConstant(rem->InputAt(1)));
4462 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4463 break;
4464
4465 case Primitive::kPrimLong: {
4466 InvokeRuntimeCallingConvention calling_convention;
4467 locations->SetInAt(0, Location::RegisterPairLocation(
4468 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1)));
4469 locations->SetInAt(1, Location::RegisterPairLocation(
4470 calling_convention.GetRegisterAt(2), calling_convention.GetRegisterAt(3)));
4471 locations->SetOut(calling_convention.GetReturnLocation(type));
4472 break;
4473 }
4474
4475 case Primitive::kPrimFloat:
4476 case Primitive::kPrimDouble: {
4477 InvokeRuntimeCallingConvention calling_convention;
4478 locations->SetInAt(0, Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(0)));
4479 locations->SetInAt(1, Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(1)));
4480 locations->SetOut(calling_convention.GetReturnLocation(type));
4481 break;
4482 }
4483
4484 default:
4485 LOG(FATAL) << "Unexpected rem type " << type;
4486 }
4487 }
4488
VisitRem(HRem * instruction)4489 void InstructionCodeGeneratorMIPS::VisitRem(HRem* instruction) {
4490 Primitive::Type type = instruction->GetType();
4491
4492 switch (type) {
4493 case Primitive::kPrimInt:
4494 GenerateDivRemIntegral(instruction);
4495 break;
4496 case Primitive::kPrimLong: {
4497 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pLmod),
4498 instruction,
4499 instruction->GetDexPc(),
4500 nullptr,
4501 IsDirectEntrypoint(kQuickLmod));
4502 CheckEntrypointTypes<kQuickLmod, int64_t, int64_t, int64_t>();
4503 break;
4504 }
4505 case Primitive::kPrimFloat: {
4506 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pFmodf),
4507 instruction, instruction->GetDexPc(),
4508 nullptr,
4509 IsDirectEntrypoint(kQuickFmodf));
4510 CheckEntrypointTypes<kQuickFmodf, float, float, float>();
4511 break;
4512 }
4513 case Primitive::kPrimDouble: {
4514 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pFmod),
4515 instruction, instruction->GetDexPc(),
4516 nullptr,
4517 IsDirectEntrypoint(kQuickFmod));
4518 CheckEntrypointTypes<kQuickFmod, double, double, double>();
4519 break;
4520 }
4521 default:
4522 LOG(FATAL) << "Unexpected rem type " << type;
4523 }
4524 }
4525
VisitMemoryBarrier(HMemoryBarrier * memory_barrier)4526 void LocationsBuilderMIPS::VisitMemoryBarrier(HMemoryBarrier* memory_barrier) {
4527 memory_barrier->SetLocations(nullptr);
4528 }
4529
VisitMemoryBarrier(HMemoryBarrier * memory_barrier)4530 void InstructionCodeGeneratorMIPS::VisitMemoryBarrier(HMemoryBarrier* memory_barrier) {
4531 GenerateMemoryBarrier(memory_barrier->GetBarrierKind());
4532 }
4533
VisitReturn(HReturn * ret)4534 void LocationsBuilderMIPS::VisitReturn(HReturn* ret) {
4535 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(ret);
4536 Primitive::Type return_type = ret->InputAt(0)->GetType();
4537 locations->SetInAt(0, MipsReturnLocation(return_type));
4538 }
4539
VisitReturn(HReturn * ret ATTRIBUTE_UNUSED)4540 void InstructionCodeGeneratorMIPS::VisitReturn(HReturn* ret ATTRIBUTE_UNUSED) {
4541 codegen_->GenerateFrameExit();
4542 }
4543
VisitReturnVoid(HReturnVoid * ret)4544 void LocationsBuilderMIPS::VisitReturnVoid(HReturnVoid* ret) {
4545 ret->SetLocations(nullptr);
4546 }
4547
VisitReturnVoid(HReturnVoid * ret ATTRIBUTE_UNUSED)4548 void InstructionCodeGeneratorMIPS::VisitReturnVoid(HReturnVoid* ret ATTRIBUTE_UNUSED) {
4549 codegen_->GenerateFrameExit();
4550 }
4551
VisitRor(HRor * ror)4552 void LocationsBuilderMIPS::VisitRor(HRor* ror) {
4553 HandleShift(ror);
4554 }
4555
VisitRor(HRor * ror)4556 void InstructionCodeGeneratorMIPS::VisitRor(HRor* ror) {
4557 HandleShift(ror);
4558 }
4559
VisitShl(HShl * shl)4560 void LocationsBuilderMIPS::VisitShl(HShl* shl) {
4561 HandleShift(shl);
4562 }
4563
VisitShl(HShl * shl)4564 void InstructionCodeGeneratorMIPS::VisitShl(HShl* shl) {
4565 HandleShift(shl);
4566 }
4567
VisitShr(HShr * shr)4568 void LocationsBuilderMIPS::VisitShr(HShr* shr) {
4569 HandleShift(shr);
4570 }
4571
VisitShr(HShr * shr)4572 void InstructionCodeGeneratorMIPS::VisitShr(HShr* shr) {
4573 HandleShift(shr);
4574 }
4575
VisitSub(HSub * instruction)4576 void LocationsBuilderMIPS::VisitSub(HSub* instruction) {
4577 HandleBinaryOp(instruction);
4578 }
4579
VisitSub(HSub * instruction)4580 void InstructionCodeGeneratorMIPS::VisitSub(HSub* instruction) {
4581 HandleBinaryOp(instruction);
4582 }
4583
VisitStaticFieldGet(HStaticFieldGet * instruction)4584 void LocationsBuilderMIPS::VisitStaticFieldGet(HStaticFieldGet* instruction) {
4585 HandleFieldGet(instruction, instruction->GetFieldInfo());
4586 }
4587
VisitStaticFieldGet(HStaticFieldGet * instruction)4588 void InstructionCodeGeneratorMIPS::VisitStaticFieldGet(HStaticFieldGet* instruction) {
4589 HandleFieldGet(instruction, instruction->GetFieldInfo(), instruction->GetDexPc());
4590 }
4591
VisitStaticFieldSet(HStaticFieldSet * instruction)4592 void LocationsBuilderMIPS::VisitStaticFieldSet(HStaticFieldSet* instruction) {
4593 HandleFieldSet(instruction, instruction->GetFieldInfo());
4594 }
4595
VisitStaticFieldSet(HStaticFieldSet * instruction)4596 void InstructionCodeGeneratorMIPS::VisitStaticFieldSet(HStaticFieldSet* instruction) {
4597 HandleFieldSet(instruction, instruction->GetFieldInfo(), instruction->GetDexPc());
4598 }
4599
VisitUnresolvedInstanceFieldGet(HUnresolvedInstanceFieldGet * instruction)4600 void LocationsBuilderMIPS::VisitUnresolvedInstanceFieldGet(
4601 HUnresolvedInstanceFieldGet* instruction) {
4602 FieldAccessCallingConventionMIPS calling_convention;
4603 codegen_->CreateUnresolvedFieldLocationSummary(instruction,
4604 instruction->GetFieldType(),
4605 calling_convention);
4606 }
4607
VisitUnresolvedInstanceFieldGet(HUnresolvedInstanceFieldGet * instruction)4608 void InstructionCodeGeneratorMIPS::VisitUnresolvedInstanceFieldGet(
4609 HUnresolvedInstanceFieldGet* instruction) {
4610 FieldAccessCallingConventionMIPS calling_convention;
4611 codegen_->GenerateUnresolvedFieldAccess(instruction,
4612 instruction->GetFieldType(),
4613 instruction->GetFieldIndex(),
4614 instruction->GetDexPc(),
4615 calling_convention);
4616 }
4617
VisitUnresolvedInstanceFieldSet(HUnresolvedInstanceFieldSet * instruction)4618 void LocationsBuilderMIPS::VisitUnresolvedInstanceFieldSet(
4619 HUnresolvedInstanceFieldSet* instruction) {
4620 FieldAccessCallingConventionMIPS calling_convention;
4621 codegen_->CreateUnresolvedFieldLocationSummary(instruction,
4622 instruction->GetFieldType(),
4623 calling_convention);
4624 }
4625
VisitUnresolvedInstanceFieldSet(HUnresolvedInstanceFieldSet * instruction)4626 void InstructionCodeGeneratorMIPS::VisitUnresolvedInstanceFieldSet(
4627 HUnresolvedInstanceFieldSet* instruction) {
4628 FieldAccessCallingConventionMIPS calling_convention;
4629 codegen_->GenerateUnresolvedFieldAccess(instruction,
4630 instruction->GetFieldType(),
4631 instruction->GetFieldIndex(),
4632 instruction->GetDexPc(),
4633 calling_convention);
4634 }
4635
VisitUnresolvedStaticFieldGet(HUnresolvedStaticFieldGet * instruction)4636 void LocationsBuilderMIPS::VisitUnresolvedStaticFieldGet(
4637 HUnresolvedStaticFieldGet* instruction) {
4638 FieldAccessCallingConventionMIPS calling_convention;
4639 codegen_->CreateUnresolvedFieldLocationSummary(instruction,
4640 instruction->GetFieldType(),
4641 calling_convention);
4642 }
4643
VisitUnresolvedStaticFieldGet(HUnresolvedStaticFieldGet * instruction)4644 void InstructionCodeGeneratorMIPS::VisitUnresolvedStaticFieldGet(
4645 HUnresolvedStaticFieldGet* instruction) {
4646 FieldAccessCallingConventionMIPS calling_convention;
4647 codegen_->GenerateUnresolvedFieldAccess(instruction,
4648 instruction->GetFieldType(),
4649 instruction->GetFieldIndex(),
4650 instruction->GetDexPc(),
4651 calling_convention);
4652 }
4653
VisitUnresolvedStaticFieldSet(HUnresolvedStaticFieldSet * instruction)4654 void LocationsBuilderMIPS::VisitUnresolvedStaticFieldSet(
4655 HUnresolvedStaticFieldSet* instruction) {
4656 FieldAccessCallingConventionMIPS calling_convention;
4657 codegen_->CreateUnresolvedFieldLocationSummary(instruction,
4658 instruction->GetFieldType(),
4659 calling_convention);
4660 }
4661
VisitUnresolvedStaticFieldSet(HUnresolvedStaticFieldSet * instruction)4662 void InstructionCodeGeneratorMIPS::VisitUnresolvedStaticFieldSet(
4663 HUnresolvedStaticFieldSet* instruction) {
4664 FieldAccessCallingConventionMIPS calling_convention;
4665 codegen_->GenerateUnresolvedFieldAccess(instruction,
4666 instruction->GetFieldType(),
4667 instruction->GetFieldIndex(),
4668 instruction->GetDexPc(),
4669 calling_convention);
4670 }
4671
VisitSuspendCheck(HSuspendCheck * instruction)4672 void LocationsBuilderMIPS::VisitSuspendCheck(HSuspendCheck* instruction) {
4673 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCallOnSlowPath);
4674 }
4675
VisitSuspendCheck(HSuspendCheck * instruction)4676 void InstructionCodeGeneratorMIPS::VisitSuspendCheck(HSuspendCheck* instruction) {
4677 HBasicBlock* block = instruction->GetBlock();
4678 if (block->GetLoopInformation() != nullptr) {
4679 DCHECK(block->GetLoopInformation()->GetSuspendCheck() == instruction);
4680 // The back edge will generate the suspend check.
4681 return;
4682 }
4683 if (block->IsEntryBlock() && instruction->GetNext()->IsGoto()) {
4684 // The goto will generate the suspend check.
4685 return;
4686 }
4687 GenerateSuspendCheck(instruction, nullptr);
4688 }
4689
VisitThrow(HThrow * instruction)4690 void LocationsBuilderMIPS::VisitThrow(HThrow* instruction) {
4691 LocationSummary* locations =
4692 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kCall);
4693 InvokeRuntimeCallingConvention calling_convention;
4694 locations->SetInAt(0, Location::RegisterLocation(calling_convention.GetRegisterAt(0)));
4695 }
4696
VisitThrow(HThrow * instruction)4697 void InstructionCodeGeneratorMIPS::VisitThrow(HThrow* instruction) {
4698 codegen_->InvokeRuntime(QUICK_ENTRY_POINT(pDeliverException),
4699 instruction,
4700 instruction->GetDexPc(),
4701 nullptr,
4702 IsDirectEntrypoint(kQuickDeliverException));
4703 CheckEntrypointTypes<kQuickDeliverException, void, mirror::Object*>();
4704 }
4705
VisitTypeConversion(HTypeConversion * conversion)4706 void LocationsBuilderMIPS::VisitTypeConversion(HTypeConversion* conversion) {
4707 Primitive::Type input_type = conversion->GetInputType();
4708 Primitive::Type result_type = conversion->GetResultType();
4709 DCHECK_NE(input_type, result_type);
4710 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
4711
4712 if ((input_type == Primitive::kPrimNot) || (input_type == Primitive::kPrimVoid) ||
4713 (result_type == Primitive::kPrimNot) || (result_type == Primitive::kPrimVoid)) {
4714 LOG(FATAL) << "Unexpected type conversion from " << input_type << " to " << result_type;
4715 }
4716
4717 LocationSummary::CallKind call_kind = LocationSummary::kNoCall;
4718 if (!isR6 &&
4719 ((Primitive::IsFloatingPointType(result_type) && input_type == Primitive::kPrimLong) ||
4720 (result_type == Primitive::kPrimLong && Primitive::IsFloatingPointType(input_type)))) {
4721 call_kind = LocationSummary::kCall;
4722 }
4723
4724 LocationSummary* locations = new (GetGraph()->GetArena()) LocationSummary(conversion, call_kind);
4725
4726 if (call_kind == LocationSummary::kNoCall) {
4727 if (Primitive::IsFloatingPointType(input_type)) {
4728 locations->SetInAt(0, Location::RequiresFpuRegister());
4729 } else {
4730 locations->SetInAt(0, Location::RequiresRegister());
4731 }
4732
4733 if (Primitive::IsFloatingPointType(result_type)) {
4734 locations->SetOut(Location::RequiresFpuRegister(), Location::kNoOutputOverlap);
4735 } else {
4736 locations->SetOut(Location::RequiresRegister(), Location::kNoOutputOverlap);
4737 }
4738 } else {
4739 InvokeRuntimeCallingConvention calling_convention;
4740
4741 if (Primitive::IsFloatingPointType(input_type)) {
4742 locations->SetInAt(0, Location::FpuRegisterLocation(calling_convention.GetFpuRegisterAt(0)));
4743 } else {
4744 DCHECK_EQ(input_type, Primitive::kPrimLong);
4745 locations->SetInAt(0, Location::RegisterPairLocation(
4746 calling_convention.GetRegisterAt(0), calling_convention.GetRegisterAt(1)));
4747 }
4748
4749 locations->SetOut(calling_convention.GetReturnLocation(result_type));
4750 }
4751 }
4752
VisitTypeConversion(HTypeConversion * conversion)4753 void InstructionCodeGeneratorMIPS::VisitTypeConversion(HTypeConversion* conversion) {
4754 LocationSummary* locations = conversion->GetLocations();
4755 Primitive::Type result_type = conversion->GetResultType();
4756 Primitive::Type input_type = conversion->GetInputType();
4757 bool has_sign_extension = codegen_->GetInstructionSetFeatures().IsMipsIsaRevGreaterThanEqual2();
4758 bool isR6 = codegen_->GetInstructionSetFeatures().IsR6();
4759 bool fpu_32bit = codegen_->GetInstructionSetFeatures().Is32BitFloatingPoint();
4760
4761 DCHECK_NE(input_type, result_type);
4762
4763 if (result_type == Primitive::kPrimLong && Primitive::IsIntegralType(input_type)) {
4764 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4765 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4766 Register src = locations->InAt(0).AsRegister<Register>();
4767
4768 __ Move(dst_low, src);
4769 __ Sra(dst_high, src, 31);
4770 } else if (Primitive::IsIntegralType(result_type) && Primitive::IsIntegralType(input_type)) {
4771 Register dst = locations->Out().AsRegister<Register>();
4772 Register src = (input_type == Primitive::kPrimLong)
4773 ? locations->InAt(0).AsRegisterPairLow<Register>()
4774 : locations->InAt(0).AsRegister<Register>();
4775
4776 switch (result_type) {
4777 case Primitive::kPrimChar:
4778 __ Andi(dst, src, 0xFFFF);
4779 break;
4780 case Primitive::kPrimByte:
4781 if (has_sign_extension) {
4782 __ Seb(dst, src);
4783 } else {
4784 __ Sll(dst, src, 24);
4785 __ Sra(dst, dst, 24);
4786 }
4787 break;
4788 case Primitive::kPrimShort:
4789 if (has_sign_extension) {
4790 __ Seh(dst, src);
4791 } else {
4792 __ Sll(dst, src, 16);
4793 __ Sra(dst, dst, 16);
4794 }
4795 break;
4796 case Primitive::kPrimInt:
4797 __ Move(dst, src);
4798 break;
4799
4800 default:
4801 LOG(FATAL) << "Unexpected type conversion from " << input_type
4802 << " to " << result_type;
4803 }
4804 } else if (Primitive::IsFloatingPointType(result_type) && Primitive::IsIntegralType(input_type)) {
4805 if (input_type == Primitive::kPrimLong) {
4806 if (isR6) {
4807 // cvt.s.l/cvt.d.l requires MIPSR2+ with FR=1. MIPS32R6 is implemented as a secondary
4808 // architecture on top of MIPS64R6, which has FR=1, and therefore can use the instruction.
4809 Register src_high = locations->InAt(0).AsRegisterPairHigh<Register>();
4810 Register src_low = locations->InAt(0).AsRegisterPairLow<Register>();
4811 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4812 __ Mtc1(src_low, FTMP);
4813 __ Mthc1(src_high, FTMP);
4814 if (result_type == Primitive::kPrimFloat) {
4815 __ Cvtsl(dst, FTMP);
4816 } else {
4817 __ Cvtdl(dst, FTMP);
4818 }
4819 } else {
4820 int32_t entry_offset = (result_type == Primitive::kPrimFloat) ? QUICK_ENTRY_POINT(pL2f)
4821 : QUICK_ENTRY_POINT(pL2d);
4822 bool direct = (result_type == Primitive::kPrimFloat) ? IsDirectEntrypoint(kQuickL2f)
4823 : IsDirectEntrypoint(kQuickL2d);
4824 codegen_->InvokeRuntime(entry_offset,
4825 conversion,
4826 conversion->GetDexPc(),
4827 nullptr,
4828 direct);
4829 if (result_type == Primitive::kPrimFloat) {
4830 CheckEntrypointTypes<kQuickL2f, float, int64_t>();
4831 } else {
4832 CheckEntrypointTypes<kQuickL2d, double, int64_t>();
4833 }
4834 }
4835 } else {
4836 Register src = locations->InAt(0).AsRegister<Register>();
4837 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4838 __ Mtc1(src, FTMP);
4839 if (result_type == Primitive::kPrimFloat) {
4840 __ Cvtsw(dst, FTMP);
4841 } else {
4842 __ Cvtdw(dst, FTMP);
4843 }
4844 }
4845 } else if (Primitive::IsIntegralType(result_type) && Primitive::IsFloatingPointType(input_type)) {
4846 CHECK(result_type == Primitive::kPrimInt || result_type == Primitive::kPrimLong);
4847 if (result_type == Primitive::kPrimLong) {
4848 if (isR6) {
4849 // trunc.l.s/trunc.l.d requires MIPSR2+ with FR=1. MIPS32R6 is implemented as a secondary
4850 // architecture on top of MIPS64R6, which has FR=1, and therefore can use the instruction.
4851 FRegister src = locations->InAt(0).AsFpuRegister<FRegister>();
4852 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4853 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4854 MipsLabel truncate;
4855 MipsLabel done;
4856
4857 // When NAN2008=0 (R2 and before), the truncate instruction produces the maximum positive
4858 // value when the input is either a NaN or is outside of the range of the output type
4859 // after the truncation. IOW, the three special cases (NaN, too small, too big) produce
4860 // the same result.
4861 //
4862 // When NAN2008=1 (R6), the truncate instruction caps the output at the minimum/maximum
4863 // value of the output type if the input is outside of the range after the truncation or
4864 // produces 0 when the input is a NaN. IOW, the three special cases produce three distinct
4865 // results. This matches the desired float/double-to-int/long conversion exactly.
4866 //
4867 // So, NAN2008 affects handling of negative values and NaNs by the truncate instruction.
4868 //
4869 // The following code supports both NAN2008=0 and NAN2008=1 behaviors of the truncate
4870 // instruction, the reason being that the emulator implements NAN2008=0 on MIPS64R6,
4871 // even though it must be NAN2008=1 on R6.
4872 //
4873 // The code takes care of the different behaviors by first comparing the input to the
4874 // minimum output value (-2**-63 for truncating to long, -2**-31 for truncating to int).
4875 // If the input is greater than or equal to the minimum, it procedes to the truncate
4876 // instruction, which will handle such an input the same way irrespective of NAN2008.
4877 // Otherwise the input is compared to itself to determine whether it is a NaN or not
4878 // in order to return either zero or the minimum value.
4879 //
4880 // TODO: simplify this when the emulator correctly implements NAN2008=1 behavior of the
4881 // truncate instruction for MIPS64R6.
4882 if (input_type == Primitive::kPrimFloat) {
4883 uint32_t min_val = bit_cast<uint32_t, float>(std::numeric_limits<int64_t>::min());
4884 __ LoadConst32(TMP, min_val);
4885 __ Mtc1(TMP, FTMP);
4886 __ CmpLeS(FTMP, FTMP, src);
4887 } else {
4888 uint64_t min_val = bit_cast<uint64_t, double>(std::numeric_limits<int64_t>::min());
4889 __ LoadConst32(TMP, High32Bits(min_val));
4890 __ Mtc1(ZERO, FTMP);
4891 __ Mthc1(TMP, FTMP);
4892 __ CmpLeD(FTMP, FTMP, src);
4893 }
4894
4895 __ Bc1nez(FTMP, &truncate);
4896
4897 if (input_type == Primitive::kPrimFloat) {
4898 __ CmpEqS(FTMP, src, src);
4899 } else {
4900 __ CmpEqD(FTMP, src, src);
4901 }
4902 __ Move(dst_low, ZERO);
4903 __ LoadConst32(dst_high, std::numeric_limits<int32_t>::min());
4904 __ Mfc1(TMP, FTMP);
4905 __ And(dst_high, dst_high, TMP);
4906
4907 __ B(&done);
4908
4909 __ Bind(&truncate);
4910
4911 if (input_type == Primitive::kPrimFloat) {
4912 __ TruncLS(FTMP, src);
4913 } else {
4914 __ TruncLD(FTMP, src);
4915 }
4916 __ Mfc1(dst_low, FTMP);
4917 __ Mfhc1(dst_high, FTMP);
4918
4919 __ Bind(&done);
4920 } else {
4921 int32_t entry_offset = (input_type == Primitive::kPrimFloat) ? QUICK_ENTRY_POINT(pF2l)
4922 : QUICK_ENTRY_POINT(pD2l);
4923 bool direct = (result_type == Primitive::kPrimFloat) ? IsDirectEntrypoint(kQuickF2l)
4924 : IsDirectEntrypoint(kQuickD2l);
4925 codegen_->InvokeRuntime(entry_offset, conversion, conversion->GetDexPc(), nullptr, direct);
4926 if (input_type == Primitive::kPrimFloat) {
4927 CheckEntrypointTypes<kQuickF2l, int64_t, float>();
4928 } else {
4929 CheckEntrypointTypes<kQuickD2l, int64_t, double>();
4930 }
4931 }
4932 } else {
4933 FRegister src = locations->InAt(0).AsFpuRegister<FRegister>();
4934 Register dst = locations->Out().AsRegister<Register>();
4935 MipsLabel truncate;
4936 MipsLabel done;
4937
4938 // The following code supports both NAN2008=0 and NAN2008=1 behaviors of the truncate
4939 // instruction, the reason being that the emulator implements NAN2008=0 on MIPS64R6,
4940 // even though it must be NAN2008=1 on R6.
4941 //
4942 // For details see the large comment above for the truncation of float/double to long on R6.
4943 //
4944 // TODO: simplify this when the emulator correctly implements NAN2008=1 behavior of the
4945 // truncate instruction for MIPS64R6.
4946 if (input_type == Primitive::kPrimFloat) {
4947 uint32_t min_val = bit_cast<uint32_t, float>(std::numeric_limits<int32_t>::min());
4948 __ LoadConst32(TMP, min_val);
4949 __ Mtc1(TMP, FTMP);
4950 } else {
4951 uint64_t min_val = bit_cast<uint64_t, double>(std::numeric_limits<int32_t>::min());
4952 __ LoadConst32(TMP, High32Bits(min_val));
4953 __ Mtc1(ZERO, FTMP);
4954 if (fpu_32bit) {
4955 __ Mtc1(TMP, static_cast<FRegister>(FTMP + 1));
4956 } else {
4957 __ Mthc1(TMP, FTMP);
4958 }
4959 }
4960
4961 if (isR6) {
4962 if (input_type == Primitive::kPrimFloat) {
4963 __ CmpLeS(FTMP, FTMP, src);
4964 } else {
4965 __ CmpLeD(FTMP, FTMP, src);
4966 }
4967 __ Bc1nez(FTMP, &truncate);
4968
4969 if (input_type == Primitive::kPrimFloat) {
4970 __ CmpEqS(FTMP, src, src);
4971 } else {
4972 __ CmpEqD(FTMP, src, src);
4973 }
4974 __ LoadConst32(dst, std::numeric_limits<int32_t>::min());
4975 __ Mfc1(TMP, FTMP);
4976 __ And(dst, dst, TMP);
4977 } else {
4978 if (input_type == Primitive::kPrimFloat) {
4979 __ ColeS(0, FTMP, src);
4980 } else {
4981 __ ColeD(0, FTMP, src);
4982 }
4983 __ Bc1t(0, &truncate);
4984
4985 if (input_type == Primitive::kPrimFloat) {
4986 __ CeqS(0, src, src);
4987 } else {
4988 __ CeqD(0, src, src);
4989 }
4990 __ LoadConst32(dst, std::numeric_limits<int32_t>::min());
4991 __ Movf(dst, ZERO, 0);
4992 }
4993
4994 __ B(&done);
4995
4996 __ Bind(&truncate);
4997
4998 if (input_type == Primitive::kPrimFloat) {
4999 __ TruncWS(FTMP, src);
5000 } else {
5001 __ TruncWD(FTMP, src);
5002 }
5003 __ Mfc1(dst, FTMP);
5004
5005 __ Bind(&done);
5006 }
5007 } else if (Primitive::IsFloatingPointType(result_type) &&
5008 Primitive::IsFloatingPointType(input_type)) {
5009 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
5010 FRegister src = locations->InAt(0).AsFpuRegister<FRegister>();
5011 if (result_type == Primitive::kPrimFloat) {
5012 __ Cvtsd(dst, src);
5013 } else {
5014 __ Cvtds(dst, src);
5015 }
5016 } else {
5017 LOG(FATAL) << "Unexpected or unimplemented type conversion from " << input_type
5018 << " to " << result_type;
5019 }
5020 }
5021
VisitUShr(HUShr * ushr)5022 void LocationsBuilderMIPS::VisitUShr(HUShr* ushr) {
5023 HandleShift(ushr);
5024 }
5025
VisitUShr(HUShr * ushr)5026 void InstructionCodeGeneratorMIPS::VisitUShr(HUShr* ushr) {
5027 HandleShift(ushr);
5028 }
5029
VisitXor(HXor * instruction)5030 void LocationsBuilderMIPS::VisitXor(HXor* instruction) {
5031 HandleBinaryOp(instruction);
5032 }
5033
VisitXor(HXor * instruction)5034 void InstructionCodeGeneratorMIPS::VisitXor(HXor* instruction) {
5035 HandleBinaryOp(instruction);
5036 }
5037
VisitBoundType(HBoundType * instruction ATTRIBUTE_UNUSED)5038 void LocationsBuilderMIPS::VisitBoundType(HBoundType* instruction ATTRIBUTE_UNUSED) {
5039 // Nothing to do, this should be removed during prepare for register allocator.
5040 LOG(FATAL) << "Unreachable";
5041 }
5042
VisitBoundType(HBoundType * instruction ATTRIBUTE_UNUSED)5043 void InstructionCodeGeneratorMIPS::VisitBoundType(HBoundType* instruction ATTRIBUTE_UNUSED) {
5044 // Nothing to do, this should be removed during prepare for register allocator.
5045 LOG(FATAL) << "Unreachable";
5046 }
5047
VisitEqual(HEqual * comp)5048 void LocationsBuilderMIPS::VisitEqual(HEqual* comp) {
5049 HandleCondition(comp);
5050 }
5051
VisitEqual(HEqual * comp)5052 void InstructionCodeGeneratorMIPS::VisitEqual(HEqual* comp) {
5053 HandleCondition(comp);
5054 }
5055
VisitNotEqual(HNotEqual * comp)5056 void LocationsBuilderMIPS::VisitNotEqual(HNotEqual* comp) {
5057 HandleCondition(comp);
5058 }
5059
VisitNotEqual(HNotEqual * comp)5060 void InstructionCodeGeneratorMIPS::VisitNotEqual(HNotEqual* comp) {
5061 HandleCondition(comp);
5062 }
5063
VisitLessThan(HLessThan * comp)5064 void LocationsBuilderMIPS::VisitLessThan(HLessThan* comp) {
5065 HandleCondition(comp);
5066 }
5067
VisitLessThan(HLessThan * comp)5068 void InstructionCodeGeneratorMIPS::VisitLessThan(HLessThan* comp) {
5069 HandleCondition(comp);
5070 }
5071
VisitLessThanOrEqual(HLessThanOrEqual * comp)5072 void LocationsBuilderMIPS::VisitLessThanOrEqual(HLessThanOrEqual* comp) {
5073 HandleCondition(comp);
5074 }
5075
VisitLessThanOrEqual(HLessThanOrEqual * comp)5076 void InstructionCodeGeneratorMIPS::VisitLessThanOrEqual(HLessThanOrEqual* comp) {
5077 HandleCondition(comp);
5078 }
5079
VisitGreaterThan(HGreaterThan * comp)5080 void LocationsBuilderMIPS::VisitGreaterThan(HGreaterThan* comp) {
5081 HandleCondition(comp);
5082 }
5083
VisitGreaterThan(HGreaterThan * comp)5084 void InstructionCodeGeneratorMIPS::VisitGreaterThan(HGreaterThan* comp) {
5085 HandleCondition(comp);
5086 }
5087
VisitGreaterThanOrEqual(HGreaterThanOrEqual * comp)5088 void LocationsBuilderMIPS::VisitGreaterThanOrEqual(HGreaterThanOrEqual* comp) {
5089 HandleCondition(comp);
5090 }
5091
VisitGreaterThanOrEqual(HGreaterThanOrEqual * comp)5092 void InstructionCodeGeneratorMIPS::VisitGreaterThanOrEqual(HGreaterThanOrEqual* comp) {
5093 HandleCondition(comp);
5094 }
5095
VisitBelow(HBelow * comp)5096 void LocationsBuilderMIPS::VisitBelow(HBelow* comp) {
5097 HandleCondition(comp);
5098 }
5099
VisitBelow(HBelow * comp)5100 void InstructionCodeGeneratorMIPS::VisitBelow(HBelow* comp) {
5101 HandleCondition(comp);
5102 }
5103
VisitBelowOrEqual(HBelowOrEqual * comp)5104 void LocationsBuilderMIPS::VisitBelowOrEqual(HBelowOrEqual* comp) {
5105 HandleCondition(comp);
5106 }
5107
VisitBelowOrEqual(HBelowOrEqual * comp)5108 void InstructionCodeGeneratorMIPS::VisitBelowOrEqual(HBelowOrEqual* comp) {
5109 HandleCondition(comp);
5110 }
5111
VisitAbove(HAbove * comp)5112 void LocationsBuilderMIPS::VisitAbove(HAbove* comp) {
5113 HandleCondition(comp);
5114 }
5115
VisitAbove(HAbove * comp)5116 void InstructionCodeGeneratorMIPS::VisitAbove(HAbove* comp) {
5117 HandleCondition(comp);
5118 }
5119
VisitAboveOrEqual(HAboveOrEqual * comp)5120 void LocationsBuilderMIPS::VisitAboveOrEqual(HAboveOrEqual* comp) {
5121 HandleCondition(comp);
5122 }
5123
VisitAboveOrEqual(HAboveOrEqual * comp)5124 void InstructionCodeGeneratorMIPS::VisitAboveOrEqual(HAboveOrEqual* comp) {
5125 HandleCondition(comp);
5126 }
5127
VisitPackedSwitch(HPackedSwitch * switch_instr)5128 void LocationsBuilderMIPS::VisitPackedSwitch(HPackedSwitch* switch_instr) {
5129 LocationSummary* locations =
5130 new (GetGraph()->GetArena()) LocationSummary(switch_instr, LocationSummary::kNoCall);
5131 locations->SetInAt(0, Location::RequiresRegister());
5132 }
5133
VisitPackedSwitch(HPackedSwitch * switch_instr)5134 void InstructionCodeGeneratorMIPS::VisitPackedSwitch(HPackedSwitch* switch_instr) {
5135 int32_t lower_bound = switch_instr->GetStartValue();
5136 int32_t num_entries = switch_instr->GetNumEntries();
5137 LocationSummary* locations = switch_instr->GetLocations();
5138 Register value_reg = locations->InAt(0).AsRegister<Register>();
5139 HBasicBlock* default_block = switch_instr->GetDefaultBlock();
5140
5141 // Create a set of compare/jumps.
5142 Register temp_reg = TMP;
5143 __ Addiu32(temp_reg, value_reg, -lower_bound);
5144 // Jump to default if index is negative
5145 // Note: We don't check the case that index is positive while value < lower_bound, because in
5146 // this case, index >= num_entries must be true. So that we can save one branch instruction.
5147 __ Bltz(temp_reg, codegen_->GetLabelOf(default_block));
5148
5149 const ArenaVector<HBasicBlock*>& successors = switch_instr->GetBlock()->GetSuccessors();
5150 // Jump to successors[0] if value == lower_bound.
5151 __ Beqz(temp_reg, codegen_->GetLabelOf(successors[0]));
5152 int32_t last_index = 0;
5153 for (; num_entries - last_index > 2; last_index += 2) {
5154 __ Addiu(temp_reg, temp_reg, -2);
5155 // Jump to successors[last_index + 1] if value < case_value[last_index + 2].
5156 __ Bltz(temp_reg, codegen_->GetLabelOf(successors[last_index + 1]));
5157 // Jump to successors[last_index + 2] if value == case_value[last_index + 2].
5158 __ Beqz(temp_reg, codegen_->GetLabelOf(successors[last_index + 2]));
5159 }
5160 if (num_entries - last_index == 2) {
5161 // The last missing case_value.
5162 __ Addiu(temp_reg, temp_reg, -1);
5163 __ Beqz(temp_reg, codegen_->GetLabelOf(successors[last_index + 1]));
5164 }
5165
5166 // And the default for any other value.
5167 if (!codegen_->GoesToNextBlock(switch_instr->GetBlock(), default_block)) {
5168 __ B(codegen_->GetLabelOf(default_block));
5169 }
5170 }
5171
VisitInvokeUnresolved(HInvokeUnresolved * invoke)5172 void LocationsBuilderMIPS::VisitInvokeUnresolved(HInvokeUnresolved* invoke) {
5173 // The trampoline uses the same calling convention as dex calling conventions,
5174 // except instead of loading arg0/r0 with the target Method*, arg0/r0 will contain
5175 // the method_idx.
5176 HandleInvoke(invoke);
5177 }
5178
VisitInvokeUnresolved(HInvokeUnresolved * invoke)5179 void InstructionCodeGeneratorMIPS::VisitInvokeUnresolved(HInvokeUnresolved* invoke) {
5180 codegen_->GenerateInvokeUnresolvedRuntimeCall(invoke);
5181 }
5182
VisitClassTableGet(HClassTableGet * instruction)5183 void LocationsBuilderMIPS::VisitClassTableGet(HClassTableGet* instruction) {
5184 LocationSummary* locations =
5185 new (GetGraph()->GetArena()) LocationSummary(instruction, LocationSummary::kNoCall);
5186 locations->SetInAt(0, Location::RequiresRegister());
5187 locations->SetOut(Location::RequiresRegister());
5188 }
5189
VisitClassTableGet(HClassTableGet * instruction)5190 void InstructionCodeGeneratorMIPS::VisitClassTableGet(HClassTableGet* instruction) {
5191 LocationSummary* locations = instruction->GetLocations();
5192 if (instruction->GetTableKind() == HClassTableGet::TableKind::kVTable) {
5193 uint32_t method_offset = mirror::Class::EmbeddedVTableEntryOffset(
5194 instruction->GetIndex(), kMipsPointerSize).SizeValue();
5195 __ LoadFromOffset(kLoadWord,
5196 locations->Out().AsRegister<Register>(),
5197 locations->InAt(0).AsRegister<Register>(),
5198 method_offset);
5199 } else {
5200 uint32_t method_offset = static_cast<uint32_t>(ImTable::OffsetOfElement(
5201 instruction->GetIndex() % ImTable::kSize, kMipsPointerSize));
5202 __ LoadFromOffset(kLoadWord,
5203 locations->Out().AsRegister<Register>(),
5204 locations->InAt(0).AsRegister<Register>(),
5205 mirror::Class::ImtPtrOffset(kMipsPointerSize).Uint32Value());
5206 __ LoadFromOffset(kLoadWord,
5207 locations->Out().AsRegister<Register>(),
5208 locations->Out().AsRegister<Register>(),
5209 method_offset);
5210 }
5211 }
5212
5213 #undef __
5214 #undef QUICK_ENTRY_POINT
5215
5216 } // namespace mips
5217 } // namespace art
5218