| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 433 unsigned Reg, unsigned Lane, bool QPR) { in createDupLane()
452 unsigned DReg, unsigned Lane, in createExtractSubreg()
503 DebugLoc DL, unsigned DReg, unsigned Lane, in createInsertSubreg()
569 unsigned Lane; in optimizeAllLanesPattern() local
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| D | ARMBaseInstrInfo.cpp | 4183 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane()
4214 unsigned DReg, unsigned Lane, in getImplicitSPRUseForDPRUse()
4243 unsigned Lane; in setExecutionDomain() local
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| D | ARMExpandPseudoInsts.cpp | 510 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); in ExpandLaneOp() local
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| D | ARMISelLowering.cpp | 5946 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
6107 SDValue Lane = Op.getOperand(2); in LowerINSERT_VECTOR_ELT() local
6116 SDValue Lane = Op.getOperand(1); in LowerEXTRACT_VECTOR_ELT() local
10347 SDValue Lane = N0.getOperand(1); in PerformExtendCombine() local
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| D | ARMISelDAGToDAG.cpp | 2101 unsigned Lane = in SelectVLDSTLane() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.cpp | 153 unsigned Lane = (Offset / 4) % 64; in getSpilledReg() local
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| D | SIMachineFunctionInfo.h | 108 int Lane; member
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| D | SIISelLowering.cpp | 2204 unsigned Lane = 0; in adjustWritemask() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3057 unsigned Lane = MI->getOperand(2).getImm(); in emitCOPY_FW() local
3101 unsigned Lane = MI->getOperand(2).getImm() * 2; in emitCOPY_FD() local
3131 unsigned Lane = MI->getOperand(2).getImm(); in emitINSERT_FW() local
3167 unsigned Lane = MI->getOperand(2).getImm(); in emitINSERT_FD() local
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | SLPVectorizer.cpp | 529 int Lane; member
944 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in buildTree() local
2126 for (unsigned Lane = 0, LE = VL.size(); Lane != LE; ++Lane) { in Gather() local
2587 Value *Lane = Builder.getInt32(it->Lane); in vectorizeTree() local
2621 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in vectorizeTree() local
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| /external/gemmlowp/meta/generators/ |
| D | neon_emitter.py | 350 def Lane(self, value, lane): member in NeonEmitter
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 1796 SmallVector<Constant *, 4> Lane(Operands.size()); in ConstantFoldVectorCall() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 5376 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); in GeneratePerfectShuffle() local
5501 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
5967 for (SDValue Lane : Op->ops()) { in NormalizeBuildVector() local
6258 SDValue Lane = Value.getOperand(1); in LowerBUILD_VECTOR() local
7993 SDValue Lane = Op1.getOperand(1); in tryCombineFixedPointConvert() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 2102 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3978 uint32_t Lane = cast<ConstantInt>(Ops[2])->getZExtValue(); in EmitARMBuiltinExpr() local
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