| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 235 const MCInstrDesc &MCID) { in BuildMI()
243 const MCInstrDesc &MCID, in BuildMI()
255 const MCInstrDesc &MCID, in BuildMI()
266 const MCInstrDesc &MCID, in BuildMI()
277 const MCInstrDesc &MCID, in BuildMI()
294 const MCInstrDesc &MCID) { in BuildMI()
304 const MCInstrDesc &MCID) { in BuildMI()
314 const MCInstrDesc &MCID) { in BuildMI()
328 const MCInstrDesc &MCID) { in BuildMI()
337 const MCInstrDesc &MCID, in BuildMI()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore() local
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet() local
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother() local
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType() local
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| D | PPCRegisterInfo.cpp | 992 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister() local
1018 const MCInstrDesc &MCID = MI.getDesc(); in resolveFrameIndex() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
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| D | Thumb2SizeReduction.cpp | 220 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
567 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
717 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
780 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow() local
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| D | MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
344 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
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| D | Thumb2ITBlockPass.cpp | 155 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
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| /external/llvm/lib/CodeGen/ |
| D | ScoreboardHazardRecognizer.cpp | 129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
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| D | TargetInstrInfo.cpp | 44 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
125 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstructionImpl() local
241 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
279 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
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| D | PeepholeOptimizer.cpp | 1301 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
1321 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference() local
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| D | SystemZInstrInfo.cpp | 201 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleMove() local
624 const MCInstrDesc &MCID = MI->getDesc(); in isSimpleBD12Move() local
1158 const MCInstrDesc &MCID = get(Opcode); in getOpcodeForOffset() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 257 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits() local
418 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getExprOpValue() local
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| D | HexagonAsmBackend.cpp | 181 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable() local
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| D | HexagonMCChecker.cpp | 58 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionalCompares.cpp | 593 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
650 const MCInstrDesc &MCID = TII->get(Opc); in convert() local
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| D | AArch64RegisterInfo.cpp | 327 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); in materializeFrameBaseRegister() local
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXReplaceImageHandles.cpp | 81 const MCInstrDesc &MCID = MI.getDesc(); in processInstr() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 257 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
440 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
519 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
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| D | ScheduleDAGSDNodes.cpp | 298 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
432 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
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| D | InstrEmitter.cpp | 324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() local
856 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
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| D | ScheduleDAGRRList.cpp | 1011 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
1206 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1335 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
2701 const MCInstrDesc &MCID = TII->get(Opc); in canClobber() local
2928 const MCInstrDesc &MCID = TII->get(Opc); in AddPseudoTwoAddrDeps() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 153 const MCInstrDesc &MCID = MI->getDesc(); variable
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 101 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 535 const MCInstrDesc& MCID = PacketMI->getDesc(); in canPromoteToNewValueStore() local
745 const MCInstrDesc& MCID = PI->getDesc(); in canPromoteToDotNew() local
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