Searched defs:SubReg1 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 215 unsigned Src1 = 0, SubReg1; in isProfitableToTransform() local
308 unsigned Src1 = 0, SubReg1; in transformInstruction() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1597 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, dl, MVT::i32); in createGPRPairNode() local
1608 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createSRegPairNode() local
1619 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createDRegPairNode() local
1630 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQRegPairNode() local
1642 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, dl, MVT::i32); in createQuadSRegsNode() local
1657 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, dl, MVT::i32); in createQuadDRegsNode() local
1672 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, dl, MVT::i32); in createQuadQRegsNode() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 351 unsigned SubReg1 = MI->getOperand(1).getSubReg(); in commuteInstructionImpl() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 143 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstructionImpl() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 407 SDValue RC, SubReg0, SubReg1; in Select() local
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