1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "brw_context.h"
33 #include "brw_wm.h"
34 #include "brw_state.h"
35 #include "main/formats.h"
36 #include "main/fbobject.h"
37 #include "main/samplerobj.h"
38 #include "program/prog_parameter.h"
39
40 #include "glsl/ralloc.h"
41
42 /** Return number of src args for given instruction */
brw_wm_nr_args(GLuint opcode)43 GLuint brw_wm_nr_args( GLuint opcode )
44 {
45 switch (opcode) {
46 case WM_FRONTFACING:
47 case WM_PIXELXY:
48 return 0;
49 case WM_CINTERP:
50 case WM_WPOSXY:
51 case WM_DELTAXY:
52 return 1;
53 case WM_LINTERP:
54 case WM_PIXELW:
55 return 2;
56 case WM_FB_WRITE:
57 case WM_PINTERP:
58 return 3;
59 default:
60 assert(opcode < MAX_OPCODE);
61 return _mesa_num_inst_src_regs(opcode);
62 }
63 }
64
65
brw_wm_is_scalar_result(GLuint opcode)66 GLuint brw_wm_is_scalar_result( GLuint opcode )
67 {
68 switch (opcode) {
69 case OPCODE_COS:
70 case OPCODE_EX2:
71 case OPCODE_LG2:
72 case OPCODE_POW:
73 case OPCODE_RCP:
74 case OPCODE_RSQ:
75 case OPCODE_SIN:
76 case OPCODE_DP2:
77 case OPCODE_DP3:
78 case OPCODE_DP4:
79 case OPCODE_DPH:
80 case OPCODE_DST:
81 return 1;
82
83 default:
84 return 0;
85 }
86 }
87
88
89 /**
90 * Do GPU code generation for non-GLSL shader. non-GLSL shaders have
91 * no flow control instructions so we can more readily do SSA-style
92 * optimizations.
93 */
94 static void
brw_wm_non_glsl_emit(struct brw_context * brw,struct brw_wm_compile * c)95 brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
96 {
97 /* Augment fragment program. Add instructions for pre- and
98 * post-fragment-program tasks such as interpolation and fogging.
99 */
100 brw_wm_pass_fp(c);
101
102 /* Translate to intermediate representation. Build register usage
103 * chains.
104 */
105 brw_wm_pass0(c);
106
107 /* Dead code removal.
108 */
109 brw_wm_pass1(c);
110
111 /* Register allocation.
112 * Divide by two because we operate on 16 pixels at a time and require
113 * two GRF entries for each logical shader register.
114 */
115 c->grf_limit = BRW_WM_MAX_GRF / 2;
116
117 brw_wm_pass2(c);
118
119 /* how many general-purpose registers are used */
120 c->prog_data.reg_blocks = brw_register_blocks(c->max_wm_grf);
121
122 /* Emit GEN4 code.
123 */
124 brw_wm_emit(c);
125 }
126
127
128 /**
129 * Return a bitfield where bit n is set if barycentric interpolation mode n
130 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
131 */
132 static unsigned
brw_compute_barycentric_interp_modes(struct brw_context * brw,bool shade_model_flat,const struct gl_fragment_program * fprog)133 brw_compute_barycentric_interp_modes(struct brw_context *brw,
134 bool shade_model_flat,
135 const struct gl_fragment_program *fprog)
136 {
137 unsigned barycentric_interp_modes = 0;
138 int attr;
139
140 /* Loop through all fragment shader inputs to figure out what interpolation
141 * modes are in use, and set the appropriate bits in
142 * barycentric_interp_modes.
143 */
144 for (attr = 0; attr < FRAG_ATTRIB_MAX; ++attr) {
145 enum glsl_interp_qualifier interp_qualifier =
146 fprog->InterpQualifier[attr];
147 bool is_centroid = fprog->IsCentroid & BITFIELD64_BIT(attr);
148 bool is_gl_Color = attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1;
149
150 /* Ignore unused inputs. */
151 if (!(fprog->Base.InputsRead & BITFIELD64_BIT(attr)))
152 continue;
153
154 /* Ignore WPOS and FACE, because they don't require interpolation. */
155 if (attr == FRAG_ATTRIB_WPOS || attr == FRAG_ATTRIB_FACE)
156 continue;
157
158 /* Determine the set (or sets) of barycentric coordinates needed to
159 * interpolate this variable. Note that when
160 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
161 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
162 * for lit pixels, so we need both sets of barycentric coordinates.
163 */
164 if (interp_qualifier == INTERP_QUALIFIER_NOPERSPECTIVE) {
165 if (is_centroid) {
166 barycentric_interp_modes |=
167 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
168 }
169 if (!is_centroid || brw->needs_unlit_centroid_workaround) {
170 barycentric_interp_modes |=
171 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
172 }
173 } else if (interp_qualifier == INTERP_QUALIFIER_SMOOTH ||
174 (!(shade_model_flat && is_gl_Color) &&
175 interp_qualifier == INTERP_QUALIFIER_NONE)) {
176 if (is_centroid) {
177 barycentric_interp_modes |=
178 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
179 }
180 if (!is_centroid || brw->needs_unlit_centroid_workaround) {
181 barycentric_interp_modes |=
182 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
183 }
184 }
185 }
186
187 return barycentric_interp_modes;
188 }
189
190
191 void
brw_wm_payload_setup(struct brw_context * brw,struct brw_wm_compile * c)192 brw_wm_payload_setup(struct brw_context *brw,
193 struct brw_wm_compile *c)
194 {
195 struct intel_context *intel = &brw->intel;
196 bool uses_depth = (c->fp->program.Base.InputsRead &
197 (1 << FRAG_ATTRIB_WPOS)) != 0;
198 unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
199 int i;
200
201 if (intel->gen >= 6) {
202 /* R0-1: masks, pixel X/Y coordinates. */
203 c->nr_payload_regs = 2;
204 /* R2: only for 32-pixel dispatch.*/
205
206 /* R3-26: barycentric interpolation coordinates. These appear in the
207 * same order that they appear in the brw_wm_barycentric_interp_mode
208 * enum. Each set of coordinates occupies 2 registers if dispatch width
209 * == 8 and 4 registers if dispatch width == 16. Coordinates only
210 * appear if they were enabled using the "Barycentric Interpolation
211 * Mode" bits in WM_STATE.
212 */
213 for (i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
214 if (barycentric_interp_modes & (1 << i)) {
215 c->barycentric_coord_reg[i] = c->nr_payload_regs;
216 c->nr_payload_regs += 2;
217 if (c->dispatch_width == 16) {
218 c->nr_payload_regs += 2;
219 }
220 }
221 }
222
223 /* R27: interpolated depth if uses source depth */
224 if (uses_depth) {
225 c->source_depth_reg = c->nr_payload_regs;
226 c->nr_payload_regs++;
227 if (c->dispatch_width == 16) {
228 /* R28: interpolated depth if not 8-wide. */
229 c->nr_payload_regs++;
230 }
231 }
232 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
233 */
234 if (uses_depth) {
235 c->source_w_reg = c->nr_payload_regs;
236 c->nr_payload_regs++;
237 if (c->dispatch_width == 16) {
238 /* R30: interpolated W if not 8-wide. */
239 c->nr_payload_regs++;
240 }
241 }
242 /* R31: MSAA position offsets. */
243 /* R32-: bary for 32-pixel. */
244 /* R58-59: interp W for 32-pixel. */
245
246 if (c->fp->program.Base.OutputsWritten &
247 BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
248 c->source_depth_to_render_target = true;
249 c->computes_depth = true;
250 }
251 } else {
252 brw_wm_lookup_iz(intel, c);
253 }
254 }
255
256 /**
257 * All Mesa program -> GPU code generation goes through this function.
258 * Depending on the instructions used (i.e. flow control instructions)
259 * we'll use one of two code generators.
260 */
do_wm_prog(struct brw_context * brw,struct gl_shader_program * prog,struct brw_fragment_program * fp,struct brw_wm_prog_key * key)261 bool do_wm_prog(struct brw_context *brw,
262 struct gl_shader_program *prog,
263 struct brw_fragment_program *fp,
264 struct brw_wm_prog_key *key)
265 {
266 struct intel_context *intel = &brw->intel;
267 struct brw_wm_compile *c;
268 const GLuint *program;
269 GLuint program_size;
270
271 c = brw->wm.compile_data;
272 if (c == NULL) {
273 brw->wm.compile_data = rzalloc(NULL, struct brw_wm_compile);
274 c = brw->wm.compile_data;
275 if (c == NULL) {
276 /* Ouch - big out of memory problem. Can't continue
277 * without triggering a segfault, no way to signal,
278 * so just return.
279 */
280 return false;
281 }
282 } else {
283 void *instruction = c->instruction;
284 void *prog_instructions = c->prog_instructions;
285 void *vreg = c->vreg;
286 void *refs = c->refs;
287 memset(c, 0, sizeof(*brw->wm.compile_data));
288 c->instruction = instruction;
289 c->prog_instructions = prog_instructions;
290 c->vreg = vreg;
291 c->refs = refs;
292 }
293 memcpy(&c->key, key, sizeof(*key));
294
295 c->fp = fp;
296 c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
297
298 brw_init_compile(brw, &c->func, c);
299
300 c->prog_data.barycentric_interp_modes =
301 brw_compute_barycentric_interp_modes(brw, c->key.flat_shade,
302 &fp->program);
303
304 if (prog && prog->_LinkedShaders[MESA_SHADER_FRAGMENT]) {
305 if (!brw_wm_fs_emit(brw, c, prog))
306 return false;
307 } else {
308 if (!c->instruction) {
309 c->instruction = rzalloc_array(c, struct brw_wm_instruction, BRW_WM_MAX_INSN);
310 c->prog_instructions = rzalloc_array(c, struct prog_instruction, BRW_WM_MAX_INSN);
311 c->vreg = rzalloc_array(c, struct brw_wm_value, BRW_WM_MAX_VREG);
312 c->refs = rzalloc_array(c, struct brw_wm_ref, BRW_WM_MAX_REF);
313 }
314
315 /* Fallback for fixed function and ARB_fp shaders. */
316 c->dispatch_width = 16;
317 brw_wm_payload_setup(brw, c);
318 brw_wm_non_glsl_emit(brw, c);
319 c->prog_data.dispatch_width = 16;
320 }
321
322 /* Scratch space is used for register spilling */
323 if (c->last_scratch) {
324 perf_debug("Fragment shader triggered register spilling. "
325 "Try reducing the number of live scalar values to "
326 "improve performance.\n");
327
328 c->prog_data.total_scratch = brw_get_scratch_size(c->last_scratch);
329
330 brw_get_scratch_bo(intel, &brw->wm.scratch_bo,
331 c->prog_data.total_scratch * brw->max_wm_threads);
332 }
333
334 if (unlikely(INTEL_DEBUG & DEBUG_WM))
335 fprintf(stderr, "\n");
336
337 /* get the program
338 */
339 program = brw_get_program(&c->func, &program_size);
340
341 brw_upload_cache(&brw->cache, BRW_WM_PROG,
342 &c->key, sizeof(c->key),
343 program, program_size,
344 &c->prog_data, sizeof(c->prog_data),
345 &brw->wm.prog_offset, &brw->wm.prog_data);
346
347 return true;
348 }
349
350 static bool
key_debug(const char * name,int a,int b)351 key_debug(const char *name, int a, int b)
352 {
353 if (a != b) {
354 perf_debug(" %s %d->%d\n", name, a, b);
355 return true;
356 } else {
357 return false;
358 }
359 }
360
361 bool
brw_debug_recompile_sampler_key(const struct brw_sampler_prog_key_data * old_key,const struct brw_sampler_prog_key_data * key)362 brw_debug_recompile_sampler_key(const struct brw_sampler_prog_key_data *old_key,
363 const struct brw_sampler_prog_key_data *key)
364 {
365 bool found = false;
366
367 for (unsigned int i = 0; i < MAX_SAMPLERS; i++) {
368 found |= key_debug("EXT_texture_swizzle or DEPTH_TEXTURE_MODE",
369 old_key->swizzles[i], key->swizzles[i]);
370 }
371 found |= key_debug("GL_CLAMP enabled on any texture unit's 1st coordinate",
372 old_key->gl_clamp_mask[0], key->gl_clamp_mask[0]);
373 found |= key_debug("GL_CLAMP enabled on any texture unit's 2nd coordinate",
374 old_key->gl_clamp_mask[1], key->gl_clamp_mask[1]);
375 found |= key_debug("GL_CLAMP enabled on any texture unit's 3rd coordinate",
376 old_key->gl_clamp_mask[2], key->gl_clamp_mask[2]);
377 found |= key_debug("GL_MESA_ycbcr texturing\n",
378 old_key->yuvtex_mask, key->yuvtex_mask);
379 found |= key_debug("GL_MESA_ycbcr UV swapping\n",
380 old_key->yuvtex_swap_mask, key->yuvtex_swap_mask);
381
382 return found;
383 }
384
385 void
brw_wm_debug_recompile(struct brw_context * brw,struct gl_shader_program * prog,const struct brw_wm_prog_key * key)386 brw_wm_debug_recompile(struct brw_context *brw,
387 struct gl_shader_program *prog,
388 const struct brw_wm_prog_key *key)
389 {
390 struct brw_cache_item *c = NULL;
391 const struct brw_wm_prog_key *old_key = NULL;
392 bool found = false;
393
394 perf_debug("Recompiling fragment shader for program %d\n", prog->Name);
395
396 for (unsigned int i = 0; i < brw->cache.size; i++) {
397 for (c = brw->cache.items[i]; c; c = c->next) {
398 if (c->cache_id == BRW_WM_PROG) {
399 old_key = c->key;
400
401 if (old_key->program_string_id == key->program_string_id)
402 break;
403 }
404 }
405 if (c)
406 break;
407 }
408
409 if (!c) {
410 perf_debug(" Didn't find previous compile in the shader cache for "
411 "debug\n");
412 return;
413 }
414
415 found |= key_debug("alphatest, computed depth, depth test, or depth write",
416 old_key->iz_lookup, key->iz_lookup);
417 found |= key_debug("depth statistics", old_key->stats_wm, key->stats_wm);
418 found |= key_debug("flat shading", old_key->flat_shade, key->flat_shade);
419 found |= key_debug("number of color buffers", old_key->nr_color_regions, key->nr_color_regions);
420 found |= key_debug("rendering to FBO", old_key->render_to_fbo, key->render_to_fbo);
421 found |= key_debug("fragment color clamping", old_key->clamp_fragment_color, key->clamp_fragment_color);
422 found |= key_debug("line smoothing", old_key->line_aa, key->line_aa);
423 found |= key_debug("proj_attrib_mask", old_key->proj_attrib_mask, key->proj_attrib_mask);
424 found |= key_debug("renderbuffer height", old_key->drawable_height, key->drawable_height);
425 found |= key_debug("vertex shader outputs", old_key->vp_outputs_written, key->vp_outputs_written);
426
427 found |= brw_debug_recompile_sampler_key(&old_key->tex, &key->tex);
428
429 if (!found) {
430 perf_debug(" Something else\n");
431 }
432 }
433
434 void
brw_populate_sampler_prog_key_data(struct gl_context * ctx,const struct gl_program * prog,struct brw_sampler_prog_key_data * key)435 brw_populate_sampler_prog_key_data(struct gl_context *ctx,
436 const struct gl_program *prog,
437 struct brw_sampler_prog_key_data *key)
438 {
439 struct intel_context *intel = intel_context(ctx);
440
441 for (int s = 0; s < MAX_SAMPLERS; s++) {
442 key->swizzles[s] = SWIZZLE_NOOP;
443
444 if (!(prog->SamplersUsed & (1 << s)))
445 continue;
446
447 int unit_id = prog->SamplerUnits[s];
448 const struct gl_texture_unit *unit = &ctx->Texture.Unit[unit_id];
449
450 if (unit->_ReallyEnabled && unit->_Current->Target != GL_TEXTURE_BUFFER) {
451 const struct gl_texture_object *t = unit->_Current;
452 const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
453 struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit_id);
454
455 const bool alpha_depth = t->DepthMode == GL_ALPHA &&
456 (img->_BaseFormat == GL_DEPTH_COMPONENT ||
457 img->_BaseFormat == GL_DEPTH_STENCIL);
458
459 /* Haswell handles texture swizzling as surface format overrides
460 * (except for GL_ALPHA); all other platforms need MOVs in the shader.
461 */
462 if (!intel->is_haswell || alpha_depth)
463 key->swizzles[s] = brw_get_texture_swizzle(t);
464
465 if (img->InternalFormat == GL_YCBCR_MESA) {
466 key->yuvtex_mask |= 1 << s;
467 if (img->TexFormat == MESA_FORMAT_YCBCR)
468 key->yuvtex_swap_mask |= 1 << s;
469 }
470
471 if (sampler->MinFilter != GL_NEAREST &&
472 sampler->MagFilter != GL_NEAREST) {
473 if (sampler->WrapS == GL_CLAMP)
474 key->gl_clamp_mask[0] |= 1 << s;
475 if (sampler->WrapT == GL_CLAMP)
476 key->gl_clamp_mask[1] |= 1 << s;
477 if (sampler->WrapR == GL_CLAMP)
478 key->gl_clamp_mask[2] |= 1 << s;
479 }
480 }
481 }
482 }
483
brw_wm_populate_key(struct brw_context * brw,struct brw_wm_prog_key * key)484 static void brw_wm_populate_key( struct brw_context *brw,
485 struct brw_wm_prog_key *key )
486 {
487 struct gl_context *ctx = &brw->intel.ctx;
488 struct intel_context *intel = &brw->intel;
489 /* BRW_NEW_FRAGMENT_PROGRAM */
490 const struct brw_fragment_program *fp =
491 (struct brw_fragment_program *)brw->fragment_program;
492 const struct gl_program *prog = (struct gl_program *) brw->fragment_program;
493 GLuint lookup = 0;
494 GLuint line_aa;
495 bool program_uses_dfdy = fp->program.UsesDFdy;
496
497 memset(key, 0, sizeof(*key));
498
499 /* Build the index for table lookup
500 */
501 if (intel->gen < 6) {
502 /* _NEW_COLOR */
503 if (fp->program.UsesKill || ctx->Color.AlphaEnabled)
504 lookup |= IZ_PS_KILL_ALPHATEST_BIT;
505
506 if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
507 lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
508
509 /* _NEW_DEPTH */
510 if (ctx->Depth.Test)
511 lookup |= IZ_DEPTH_TEST_ENABLE_BIT;
512
513 if (ctx->Depth.Test && ctx->Depth.Mask) /* ?? */
514 lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
515
516 /* _NEW_STENCIL */
517 if (ctx->Stencil._Enabled) {
518 lookup |= IZ_STENCIL_TEST_ENABLE_BIT;
519
520 if (ctx->Stencil.WriteMask[0] ||
521 ctx->Stencil.WriteMask[ctx->Stencil._BackFace])
522 lookup |= IZ_STENCIL_WRITE_ENABLE_BIT;
523 }
524 key->iz_lookup = lookup;
525 }
526
527 line_aa = AA_NEVER;
528
529 /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */
530 if (ctx->Line.SmoothFlag) {
531 if (brw->intel.reduced_primitive == GL_LINES) {
532 line_aa = AA_ALWAYS;
533 }
534 else if (brw->intel.reduced_primitive == GL_TRIANGLES) {
535 if (ctx->Polygon.FrontMode == GL_LINE) {
536 line_aa = AA_SOMETIMES;
537
538 if (ctx->Polygon.BackMode == GL_LINE ||
539 (ctx->Polygon.CullFlag &&
540 ctx->Polygon.CullFaceMode == GL_BACK))
541 line_aa = AA_ALWAYS;
542 }
543 else if (ctx->Polygon.BackMode == GL_LINE) {
544 line_aa = AA_SOMETIMES;
545
546 if ((ctx->Polygon.CullFlag &&
547 ctx->Polygon.CullFaceMode == GL_FRONT))
548 line_aa = AA_ALWAYS;
549 }
550 }
551 }
552
553 key->line_aa = line_aa;
554
555 if (intel->gen < 6)
556 key->stats_wm = brw->intel.stats_wm;
557
558 /* BRW_NEW_WM_INPUT_DIMENSIONS */
559 /* Only set this for fixed function. The optimization it enables isn't
560 * useful for programs using shaders.
561 */
562 if (ctx->Shader.CurrentFragmentProgram)
563 key->proj_attrib_mask = 0xffffffff;
564 else
565 key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
566
567 /* _NEW_LIGHT */
568 key->flat_shade = (ctx->Light.ShadeModel == GL_FLAT);
569
570 /* _NEW_FRAG_CLAMP | _NEW_BUFFERS */
571 key->clamp_fragment_color = ctx->Color._ClampFragmentColor;
572
573 /* _NEW_TEXTURE */
574 brw_populate_sampler_prog_key_data(ctx, prog, &key->tex);
575
576 /* _NEW_BUFFERS */
577 /*
578 * Include the draw buffer origin and height so that we can calculate
579 * fragment position values relative to the bottom left of the drawable,
580 * from the incoming screen origin relative position we get as part of our
581 * payload.
582 *
583 * This is only needed for the WM_WPOSXY opcode when the fragment program
584 * uses the gl_FragCoord input.
585 *
586 * We could avoid recompiling by including this as a constant referenced by
587 * our program, but if we were to do that it would also be nice to handle
588 * getting that constant updated at batchbuffer submit time (when we
589 * hold the lock and know where the buffer really is) rather than at emit
590 * time when we don't hold the lock and are just guessing. We could also
591 * just avoid using this as key data if the program doesn't use
592 * fragment.position.
593 *
594 * For DRI2 the origin_x/y will always be (0,0) but we still need the
595 * drawable height in order to invert the Y axis.
596 */
597 if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
598 key->drawable_height = ctx->DrawBuffer->Height;
599 }
600
601 if ((fp->program.Base.InputsRead & FRAG_BIT_WPOS) || program_uses_dfdy) {
602 key->render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
603 }
604
605 /* _NEW_BUFFERS */
606 key->nr_color_regions = ctx->DrawBuffer->_NumColorDrawBuffers;
607 /* _NEW_MULTISAMPLE */
608 key->sample_alpha_to_coverage = ctx->Multisample.SampleAlphaToCoverage;
609
610 /* CACHE_NEW_VS_PROG */
611 if (intel->gen < 6)
612 key->vp_outputs_written = brw->vs.prog_data->outputs_written;
613
614 /* The unique fragment program ID */
615 key->program_string_id = fp->id;
616 }
617
618
619 static void
brw_upload_wm_prog(struct brw_context * brw)620 brw_upload_wm_prog(struct brw_context *brw)
621 {
622 struct intel_context *intel = &brw->intel;
623 struct gl_context *ctx = &intel->ctx;
624 struct brw_wm_prog_key key;
625 struct brw_fragment_program *fp = (struct brw_fragment_program *)
626 brw->fragment_program;
627
628 brw_wm_populate_key(brw, &key);
629
630 if (!brw_search_cache(&brw->cache, BRW_WM_PROG,
631 &key, sizeof(key),
632 &brw->wm.prog_offset, &brw->wm.prog_data)) {
633 bool success = do_wm_prog(brw, ctx->Shader._CurrentFragmentProgram, fp,
634 &key);
635 (void) success;
636 assert(success);
637 }
638 }
639
640
641 const struct brw_tracked_state brw_wm_prog = {
642 .dirty = {
643 .mesa = (_NEW_COLOR |
644 _NEW_DEPTH |
645 _NEW_STENCIL |
646 _NEW_POLYGON |
647 _NEW_LINE |
648 _NEW_LIGHT |
649 _NEW_FRAG_CLAMP |
650 _NEW_BUFFERS |
651 _NEW_TEXTURE |
652 _NEW_MULTISAMPLE),
653 .brw = (BRW_NEW_FRAGMENT_PROGRAM |
654 BRW_NEW_WM_INPUT_DIMENSIONS |
655 BRW_NEW_REDUCED_PRIMITIVE),
656 .cache = CACHE_NEW_VS_PROG,
657 },
658 .emit = brw_upload_wm_prog
659 };
660
661