1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the Mips specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H 16 17 #include "MCTargetDesc/MipsABIInfo.h" 18 #include "MipsFrameLowering.h" 19 #include "MipsISelLowering.h" 20 #include "MipsInstrInfo.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/MC/MCInstrItineraries.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Target/TargetSelectionDAGInfo.h" 25 #include "llvm/Target/TargetSubtargetInfo.h" 26 #include <string> 27 28 #define GET_SUBTARGETINFO_HEADER 29 #include "MipsGenSubtargetInfo.inc" 30 31 namespace llvm { 32 class StringRef; 33 34 class MipsTargetMachine; 35 36 class MipsSubtarget : public MipsGenSubtargetInfo { 37 virtual void anchor(); 38 39 enum MipsArchEnum { 40 MipsDefault, 41 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max, 42 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6 43 }; 44 45 enum class CPU { P5600 }; 46 47 // Mips architecture version 48 MipsArchEnum MipsArchVersion; 49 50 // Processor implementation (unused but required to exist by 51 // tablegen-erated code). 52 CPU ProcImpl; 53 54 // IsLittle - The target is Little Endian 55 bool IsLittle; 56 57 // IsSoftFloat - The target does not support any floating point instructions. 58 bool IsSoftFloat; 59 60 // IsSingleFloat - The target only supports single precision float 61 // point operations. This enable the target to use all 32 32-bit 62 // floating point registers instead of only using even ones. 63 bool IsSingleFloat; 64 65 // IsFPXX - MIPS O32 modeless ABI. 66 bool IsFPXX; 67 68 // NoABICalls - Disable SVR4-style position-independent code. 69 bool NoABICalls; 70 71 // IsFP64bit - The target processor has 64-bit floating point registers. 72 bool IsFP64bit; 73 74 /// Are odd single-precision registers permitted? 75 /// This corresponds to -modd-spreg and -mno-odd-spreg 76 bool UseOddSPReg; 77 78 // IsNan2008 - IEEE 754-2008 NaN encoding. 79 bool IsNaN2008bit; 80 81 // IsFP64bit - General-purpose registers are 64 bits wide 82 bool IsGP64bit; 83 84 // HasVFPU - Processor has a vector floating point unit. 85 bool HasVFPU; 86 87 // CPU supports cnMIPS (Cavium Networks Octeon CPU). 88 bool HasCnMips; 89 90 // isLinux - Target system is Linux. Is false we consider ELFOS for now. 91 bool IsLinux; 92 93 // UseSmallSection - Small section is used. 94 bool UseSmallSection; 95 96 /// Features related to the presence of specific instructions. 97 98 // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32 99 bool HasMips3_32; 100 101 // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2 102 bool HasMips3_32r2; 103 104 // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32 105 bool HasMips4_32; 106 107 // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2 108 bool HasMips4_32r2; 109 110 // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2 111 bool HasMips5_32r2; 112 113 // InMips16 -- can process Mips16 instructions 114 bool InMips16Mode; 115 116 // Mips16 hard float 117 bool InMips16HardFloat; 118 119 // PreviousInMips16 -- the function we just processed was in Mips 16 Mode 120 bool PreviousInMips16Mode; 121 122 // InMicroMips -- can process MicroMips instructions 123 bool InMicroMipsMode; 124 125 // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. 126 bool HasDSP, HasDSPR2, HasDSPR3; 127 128 // Allow mixed Mips16 and Mips32 in one source file 129 bool AllowMixed16_32; 130 131 // Optimize for space by compiling all functions as Mips 16 unless 132 // it needs floating point. Functions needing floating point are 133 // compiled as Mips32 134 bool Os16; 135 136 // HasMSA -- supports MSA ASE. 137 bool HasMSA; 138 139 // UseTCCInDIV -- Enables the use of trapping in the assembler. 140 bool UseTCCInDIV; 141 142 // HasEVA -- supports EVA ASE. 143 bool HasEVA; 144 145 InstrItineraryData InstrItins; 146 147 // We can override the determination of whether we are in mips16 mode 148 // as from the command line 149 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; 150 151 const MipsTargetMachine &TM; 152 153 Triple TargetTriple; 154 155 const TargetSelectionDAGInfo TSInfo; 156 std::unique_ptr<const MipsInstrInfo> InstrInfo; 157 std::unique_ptr<const MipsFrameLowering> FrameLowering; 158 std::unique_ptr<const MipsTargetLowering> TLInfo; 159 160 public: 161 /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. 162 bool enablePostRAScheduler() const override; 163 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 164 CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; 165 166 /// Only O32 and EABI supported right now. 167 bool isABI_EABI() const; 168 bool isABI_N64() const; 169 bool isABI_N32() const; 170 bool isABI_O32() const; 171 const MipsABIInfo &getABI() const; isABI_FPXX()172 bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } 173 174 /// This constructor initializes the data members to match that 175 /// of the specified triple. 176 MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 177 bool little, const MipsTargetMachine &TM); 178 179 /// ParseSubtargetFeatures - Parses features string setting specified 180 /// subtarget options. Definition of function is auto generated by tblgen. 181 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 182 hasMips1()183 bool hasMips1() const { return MipsArchVersion >= Mips1; } hasMips2()184 bool hasMips2() const { return MipsArchVersion >= Mips2; } hasMips3()185 bool hasMips3() const { return MipsArchVersion >= Mips3; } hasMips4()186 bool hasMips4() const { return MipsArchVersion >= Mips4; } hasMips5()187 bool hasMips5() const { return MipsArchVersion >= Mips5; } hasMips4_32()188 bool hasMips4_32() const { return HasMips4_32; } hasMips4_32r2()189 bool hasMips4_32r2() const { return HasMips4_32r2; } hasMips32()190 bool hasMips32() const { 191 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) || 192 hasMips64(); 193 } hasMips32r2()194 bool hasMips32r2() const { 195 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) || 196 hasMips64r2(); 197 } hasMips32r3()198 bool hasMips32r3() const { 199 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) || 200 hasMips64r2(); 201 } hasMips32r5()202 bool hasMips32r5() const { 203 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) || 204 hasMips64r5(); 205 } hasMips32r6()206 bool hasMips32r6() const { 207 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) || 208 hasMips64r6(); 209 } hasMips64()210 bool hasMips64() const { return MipsArchVersion >= Mips64; } hasMips64r2()211 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; } hasMips64r3()212 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; } hasMips64r5()213 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; } hasMips64r6()214 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; } 215 hasCnMips()216 bool hasCnMips() const { return HasCnMips; } 217 isLittle()218 bool isLittle() const { return IsLittle; } isABICalls()219 bool isABICalls() const { return !NoABICalls; } isFPXX()220 bool isFPXX() const { return IsFPXX; } isFP64bit()221 bool isFP64bit() const { return IsFP64bit; } useOddSPReg()222 bool useOddSPReg() const { return UseOddSPReg; } noOddSPReg()223 bool noOddSPReg() const { return !UseOddSPReg; } isNaN2008()224 bool isNaN2008() const { return IsNaN2008bit; } isGP64bit()225 bool isGP64bit() const { return IsGP64bit; } isGP32bit()226 bool isGP32bit() const { return !IsGP64bit; } getGPRSizeInBytes()227 unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } isSingleFloat()228 bool isSingleFloat() const { return IsSingleFloat; } hasVFPU()229 bool hasVFPU() const { return HasVFPU; } inMips16Mode()230 bool inMips16Mode() const { return InMips16Mode; } inMips16ModeDefault()231 bool inMips16ModeDefault() const { 232 return InMips16Mode; 233 } 234 // Hard float for mips16 means essentially to compile as soft float 235 // but to use a runtime library for soft float that is written with 236 // native mips32 floating point instructions (those runtime routines 237 // run in mips32 hard float mode). inMips16HardFloat()238 bool inMips16HardFloat() const { 239 return inMips16Mode() && InMips16HardFloat; 240 } inMicroMipsMode()241 bool inMicroMipsMode() const { return InMicroMipsMode; } inMicroMips32r6Mode()242 bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } inMicroMips64r6Mode()243 bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); } hasDSP()244 bool hasDSP() const { return HasDSP; } hasDSPR2()245 bool hasDSPR2() const { return HasDSPR2; } hasDSPR3()246 bool hasDSPR3() const { return HasDSPR3; } hasMSA()247 bool hasMSA() const { return HasMSA; } hasEVA()248 bool hasEVA() const { return HasEVA; } useSmallSection()249 bool useSmallSection() const { return UseSmallSection; } 250 hasStandardEncoding()251 bool hasStandardEncoding() const { return !inMips16Mode(); } 252 useSoftFloat()253 bool useSoftFloat() const { return IsSoftFloat; } 254 enableLongBranchPass()255 bool enableLongBranchPass() const { 256 return hasStandardEncoding() || allowMixed16_32(); 257 } 258 259 /// Features related to the presence of specific instructions. hasExtractInsert()260 bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } hasMTHC1()261 bool hasMTHC1() const { return hasMips32r2(); } 262 allowMixed16_32()263 bool allowMixed16_32() const { return inMips16ModeDefault() | 264 AllowMixed16_32; } 265 os16()266 bool os16() const { return Os16; } 267 isTargetNaCl()268 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 269 270 // for now constant islands are on for the whole compilation unit but we only 271 // really use them if in addition we are in mips16 mode 272 static bool useConstantIslands(); 273 stackAlignment()274 unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } 275 276 // Grab relocation model 277 Reloc::Model getRelocationModel() const; 278 279 MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, 280 const TargetMachine &TM); 281 282 /// Does the system support unaligned memory access. 283 /// 284 /// MIPS32r6/MIPS64r6 require full unaligned access support but does not 285 /// specify which component of the system provides it. Hardware, software, and 286 /// hybrid implementations are all valid. systemSupportsUnalignedAccess()287 bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } 288 289 // Set helper classes 290 void setHelperClassesMips16(); 291 void setHelperClassesMipsSE(); 292 getSelectionDAGInfo()293 const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { 294 return &TSInfo; 295 } getInstrInfo()296 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } getFrameLowering()297 const TargetFrameLowering *getFrameLowering() const override { 298 return FrameLowering.get(); 299 } getRegisterInfo()300 const MipsRegisterInfo *getRegisterInfo() const override { 301 return &InstrInfo->getRegisterInfo(); 302 } getTargetLowering()303 const MipsTargetLowering *getTargetLowering() const override { 304 return TLInfo.get(); 305 } getInstrItineraryData()306 const InstrItineraryData *getInstrItineraryData() const override { 307 return &InstrItins; 308 } 309 }; 310 } // End llvm namespace 311 312 #endif 313