1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34
35 using namespace llvm;
36
37 #define DEBUG_TYPE "arm-subtarget"
38
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #define GET_SUBTARGETINFO_CTOR
41 #include "ARMGenSubtargetInfo.inc"
42
43 static cl::opt<bool>
44 UseFusedMulOps("arm-use-mulops",
45 cl::init(true), cl::Hidden);
46
47 enum ITMode {
48 DefaultIT,
49 RestrictedIT,
50 NoRestrictedIT
51 };
52
53 static cl::opt<ITMode>
54 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
55 cl::ZeroOrMore,
56 cl::values(clEnumValN(DefaultIT, "arm-default-it",
57 "Generate IT block based on arch"),
58 clEnumValN(RestrictedIT, "arm-restrict-it",
59 "Disallow deprecated IT based on ARMv8"),
60 clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
61 "Allow IT blocks based on ARMv7"),
62 clEnumValEnd));
63
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68 cl::init(false), cl::Hidden);
69
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
initializeSubtargetDependencies(StringRef CPU,StringRef FS)72 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
73 StringRef FS) {
74 initializeEnvironment();
75 initSubtargetFeatures(CPU, FS);
76 return *this;
77 }
78
initializeFrameLowering(StringRef CPU,StringRef FS)79 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
80 StringRef FS) {
81 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
82 if (STI.isThumb1Only())
83 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
84
85 return new ARMFrameLowering(STI);
86 }
87
ARMSubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const ARMBaseTargetMachine & TM,bool IsLittle)88 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
89 const std::string &FS,
90 const ARMBaseTargetMachine &TM, bool IsLittle)
91 : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
92 ARMProcClass(None), ARMArch(ARMv4t), stackAlignment(4), CPUString(CPU),
93 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
94 FrameLowering(initializeFrameLowering(CPU, FS)),
95 // At this point initializeSubtargetDependencies has been called so
96 // we can query directly.
97 InstrInfo(isThumb1Only()
98 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
99 : !isThumb()
100 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
101 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
102 TLInfo(TM, *this) {}
103
initializeEnvironment()104 void ARMSubtarget::initializeEnvironment() {
105 HasV4TOps = false;
106 HasV5TOps = false;
107 HasV5TEOps = false;
108 HasV6Ops = false;
109 HasV6MOps = false;
110 HasV6KOps = false;
111 HasV6T2Ops = false;
112 HasV7Ops = false;
113 HasV8Ops = false;
114 HasV8_1aOps = false;
115 HasV8_2aOps = false;
116 HasVFPv2 = false;
117 HasVFPv3 = false;
118 HasVFPv4 = false;
119 HasFPARMv8 = false;
120 HasNEON = false;
121 UseNEONForSinglePrecisionFP = false;
122 UseMulOps = UseFusedMulOps;
123 SlowFPVMLx = false;
124 HasVMLxForwarding = false;
125 SlowFPBrcc = false;
126 InThumbMode = false;
127 UseSoftFloat = false;
128 HasThumb2 = false;
129 NoARM = false;
130 ReserveR9 = false;
131 NoMovt = false;
132 SupportsTailCall = false;
133 HasFP16 = false;
134 HasFullFP16 = false;
135 HasD16 = false;
136 HasHardwareDivide = false;
137 HasHardwareDivideInARM = false;
138 HasT2ExtractPack = false;
139 HasDataBarrier = false;
140 Pref32BitThumb = false;
141 AvoidCPSRPartialUpdate = false;
142 AvoidMOVsShifterOperand = false;
143 HasRAS = false;
144 HasMPExtension = false;
145 HasVirtualization = false;
146 FPOnlySP = false;
147 HasPerfMon = false;
148 HasTrustZone = false;
149 HasCrypto = false;
150 HasCRC = false;
151 HasZeroCycleZeroing = false;
152 StrictAlign = false;
153 HasDSP = false;
154 UseNaClTrap = false;
155 GenLongCalls = false;
156 UnsafeFPMath = false;
157 UseLong64 = false;
158
159 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
160 // directly from it, but we can try to make sure they're consistent when both
161 // available.
162 UseSjLjEH = isTargetDarwin() && !isTargetWatchOS();
163 assert((!TM.getMCAsmInfo() ||
164 (TM.getMCAsmInfo()->getExceptionHandlingType() ==
165 ExceptionHandling::SjLj) == UseSjLjEH) &&
166 "inconsistent sjlj choice between CodeGen and MC");
167 }
168
initSubtargetFeatures(StringRef CPU,StringRef FS)169 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
170 if (CPUString.empty()) {
171 CPUString = "generic";
172
173 if (isTargetDarwin()) {
174 StringRef ArchName = TargetTriple.getArchName();
175 if (ArchName.endswith("v7s"))
176 // Default to the Swift CPU when targeting armv7s/thumbv7s.
177 CPUString = "swift";
178 else if (ArchName.endswith("v7k"))
179 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
180 // ARMv7k does not use SjLj exception handling.
181 CPUString = "cortex-a7";
182 }
183 }
184
185 // Insert the architecture feature derived from the target triple into the
186 // feature string. This is important for setting features that are implied
187 // based on the architecture version.
188 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
189 if (!FS.empty()) {
190 if (!ArchFS.empty())
191 ArchFS = (Twine(ArchFS) + "," + FS).str();
192 else
193 ArchFS = FS;
194 }
195 ParseSubtargetFeatures(CPUString, ArchFS);
196
197 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
198 // Assert this for now to make the change obvious.
199 assert(hasV6T2Ops() || !hasThumb2());
200
201 // Keep a pointer to static instruction cost data for the specified CPU.
202 SchedModel = getSchedModelForCPU(CPUString);
203
204 // Initialize scheduling itinerary for the specified CPU.
205 InstrItins = getInstrItineraryForCPU(CPUString);
206
207 // FIXME: this is invalid for WindowsCE
208 if (isTargetWindows())
209 NoARM = true;
210
211 if (isAAPCS_ABI())
212 stackAlignment = 8;
213 if (isTargetNaCl() || isAAPCS16_ABI())
214 stackAlignment = 16;
215
216 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
217 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
218 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
219 // support in the assembler and linker to be used. This would need to be
220 // fixed to fully support tail calls in Thumb1.
221 //
222 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
223 // LR. This means if we need to reload LR, it takes an extra instructions,
224 // which outweighs the value of the tail call; but here we don't know yet
225 // whether LR is going to be used. Probably the right approach is to
226 // generate the tail call here and turn it back into CALL/RET in
227 // emitEpilogue if LR is used.
228
229 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
230 // but we need to make sure there are enough registers; the only valid
231 // registers are the 4 used for parameters. We don't currently do this
232 // case.
233
234 SupportsTailCall = !isThumb1Only();
235
236 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
237 SupportsTailCall = false;
238
239 switch (IT) {
240 case DefaultIT:
241 RestrictIT = hasV8Ops();
242 break;
243 case RestrictedIT:
244 RestrictIT = true;
245 break;
246 case NoRestrictedIT:
247 RestrictIT = false;
248 break;
249 }
250
251 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
252 const FeatureBitset &Bits = getFeatureBits();
253 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
254 (Options.UnsafeFPMath || isTargetDarwin()))
255 UseNEONForSinglePrecisionFP = true;
256 }
257
isAPCS_ABI() const258 bool ARMSubtarget::isAPCS_ABI() const {
259 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
260 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_APCS;
261 }
isAAPCS_ABI() const262 bool ARMSubtarget::isAAPCS_ABI() const {
263 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
264 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS ||
265 TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
266 }
isAAPCS16_ABI() const267 bool ARMSubtarget::isAAPCS16_ABI() const {
268 assert(TM.TargetABI != ARMBaseTargetMachine::ARM_ABI_UNKNOWN);
269 return TM.TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16;
270 }
271
272
273 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
274 bool
GVIsIndirectSymbol(const GlobalValue * GV,Reloc::Model RelocM) const275 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
276 Reloc::Model RelocM) const {
277 if (RelocM == Reloc::Static)
278 return false;
279
280 bool isDef = GV->isStrongDefinitionForLinker();
281
282 if (!isTargetMachO()) {
283 // Extra load is needed for all externally visible.
284 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
285 return false;
286 return true;
287 } else {
288 // If this is a strong reference to a definition, it is definitely not
289 // through a stub.
290 if (isDef)
291 return false;
292
293 // Unless we have a symbol with hidden visibility, we have to go through a
294 // normal $non_lazy_ptr stub because this symbol might be resolved late.
295 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
296 return true;
297
298 if (RelocM == Reloc::PIC_) {
299 // If symbol visibility is hidden, we have a stub for common symbol
300 // references and external declarations.
301 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
302 // Hidden $non_lazy_ptr reference.
303 return true;
304 }
305 }
306
307 return false;
308 }
309
getMispredictionPenalty() const310 unsigned ARMSubtarget::getMispredictionPenalty() const {
311 return SchedModel.MispredictPenalty;
312 }
313
hasSinCos() const314 bool ARMSubtarget::hasSinCos() const {
315 return isTargetWatchOS() ||
316 (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
317 }
318
enableMachineScheduler() const319 bool ARMSubtarget::enableMachineScheduler() const {
320 // Enable the MachineScheduler before register allocation for out-of-order
321 // architectures where we do not use the PostRA scheduler anymore (for now
322 // restricted to swift).
323 return getSchedModel().isOutOfOrder() && isSwift();
324 }
325
326 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
enablePostRAScheduler() const327 bool ARMSubtarget::enablePostRAScheduler() const {
328 // No need for PostRA scheduling on out of order CPUs (for now restricted to
329 // swift).
330 if (getSchedModel().isOutOfOrder() && isSwift())
331 return false;
332 return (!isThumb() || hasThumb2());
333 }
334
enableAtomicExpand() const335 bool ARMSubtarget::enableAtomicExpand() const {
336 return hasAnyDataBarrier() && !isThumb1Only();
337 }
338
useStride4VFPs(const MachineFunction & MF) const339 bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
340 // For general targets, the prologue can grow when VFPs are allocated with
341 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
342 // format which it's more important to get right.
343 return isTargetWatchOS() || (isSwift() && !MF.getFunction()->optForMinSize());
344 }
345
useMovt(const MachineFunction & MF) const346 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
347 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
348 // immediates as it is inherently position independent, and may be out of
349 // range otherwise.
350 return !NoMovt && hasV6T2Ops() &&
351 (isTargetWindows() || !MF.getFunction()->optForMinSize());
352 }
353
useFastISel() const354 bool ARMSubtarget::useFastISel() const {
355 // Enable fast-isel for any target, for testing only.
356 if (ForceFastISel)
357 return true;
358
359 // Limit fast-isel to the targets that are or have been tested.
360 if (!hasV6Ops())
361 return false;
362
363 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
364 return TM.Options.EnableFastISel &&
365 ((isTargetMachO() && !isThumb1Only()) ||
366 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
367 }
368