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Searched defs:reg (Results 1 – 25 of 88) sorted by relevance

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/art/compiler/debug/
Delf_debug_frame_writer.h45 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
53 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
68 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
76 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
92 for (int reg = 1; reg < 26; reg++) { in WriteCIE() local
100 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
118 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
129 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
142 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
152 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
/art/compiler/debug/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
117 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
139 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
151 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
159 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
168 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
191 void ALWAYS_INLINE DefCFA(Reg reg, int offset) { in DefCFA()
208 void ALWAYS_INLINE DefCFARegister(Reg reg) { in DefCFARegister()
234 void ALWAYS_INLINE ValOffset(Reg reg, int offset) { in ValOffset()
261 void ALWAYS_INLINE Expression(Reg reg, uint8_t* expr, int expr_size) { in Expression()
[all …]
/art/runtime/arch/mips64/
Dcontext_mips64.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
65 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
70 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
Dcontext_mips64.cc57 void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
64 void Mips64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/runtime/arch/arm/
Dcontext_arm.h52 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
70 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
75 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
/art/runtime/arch/x86_64/
Dcontext_x86_64.h51 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
56 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
61 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
69 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
74 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
Dasm_support_x86_64.S73 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
74 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
75 #define CFI_RESTORE(reg) .cfi_restore reg argument
76 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
82 #define CFI_DEF_CFA(reg,size) argument
83 #define CFI_DEF_CFA_REGISTER(reg) argument
84 #define CFI_RESTORE(reg) argument
85 #define CFI_REL_OFFSET(reg,size) argument
/art/runtime/arch/mips/
Dcontext_mips.h47 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
52 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
57 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
65 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
70 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
Dcontext_mips.cc57 void MipsContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
64 void MipsContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
65 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
Dassembler_x86.h85 bool IsRegister(Register reg) const { in IsRegister()
135 explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); } in Operand()
611 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
752 void PoisonHeapReference(Register reg) { negl(reg); } in PoisonHeapReference()
754 void UnpoisonHeapReference(Register reg) { negl(reg); } in UnpoisonHeapReference()
756 void MaybeUnpoisonHeapReference(Register reg) { in MaybeUnpoisonHeapReference()
826 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { in EmitRegisterOperand()
832 inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) { in EmitXmmRegisterOperand()
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
Dassembler_x86_64.h97 bool IsRegister(CpuRegister reg) const { in IsRegister()
156 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
682 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
686 void LockCmpxchgq(const Address& address, CpuRegister reg) { in LockCmpxchgq()
857 void PoisonHeapReference(CpuRegister reg) { negl(reg); } in PoisonHeapReference()
859 void UnpoisonHeapReference(CpuRegister reg) { negl(reg); } in UnpoisonHeapReference()
861 void MaybeUnpoisonHeapReference(CpuRegister reg) { in MaybeUnpoisonHeapReference()
934 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { in EmitRegisterOperand()
940 inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { in EmitXmmRegisterOperand()
Dmanaged_register_x86_64.cc40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
Dassembler_x86_64.cc27 std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) { in operator <<()
31 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { in operator <<()
35 std::ostream& operator<<(std::ostream& os, const X87Register& reg) { in operator <<()
39 void X86_64Assembler::call(CpuRegister reg) { in call()
63 void X86_64Assembler::pushq(CpuRegister reg) { in pushq()
91 void X86_64Assembler::popq(CpuRegister reg) { in popq()
1219 void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) { in xchgl()
1236 void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) { in cmpl()
1252 void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) { in cmpl()
1260 void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) { in cmpl()
[all …]
/art/runtime/arch/arm64/
Dcontext_arm64.h52 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
71 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
76 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
33 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
106 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
168 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
219 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
375 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
/art/runtime/arch/x86/
Dcontext_x86.h51 bool IsAccessibleGPR(uint32_t reg) OVERRIDE { in IsAccessibleGPR()
56 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
61 uintptr_t GetGPR(uint32_t reg) OVERRIDE { in GetGPR()
69 bool IsAccessibleFPR(uint32_t reg) OVERRIDE { in IsAccessibleFPR()
74 uintptr_t GetFPR(uint32_t reg) OVERRIDE { in GetFPR()
Dasm_support_x86.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
87 #define CFI_DEF_CFA(reg,size) argument
88 #define CFI_DEF_CFA_REGISTER(reg) argument
89 #define CFI_RESTORE(reg) argument
90 #define CFI_REL_OFFSET(reg,size) argument
/art/runtime/verifier/
Dregister_line.h365 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
374 bool SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
388 void ClearRegToLockDepth(size_t reg, size_t depth) { in ClearRegToLockDepth()
409 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()
/art/runtime/interpreter/mterp/arm/
Dheader.S196 .macro FETCH_ADVANCE_INST_RB reg argument
226 .macro GET_INST_OPCODE reg argument
241 .macro GOTO_OPCODE reg argument
244 .macro GOTO_OPCODE_BASE base,reg
/art/runtime/interpreter/mterp/arm64/
Dheader.S189 .macro FETCH_ADVANCE_INST_RB reg argument
220 .macro GET_INST_OPCODE reg argument
235 .macro GOTO_OPCODE reg argument
239 .macro GOTO_OPCODE_BASE base,reg
/art/compiler/utils/mips/
Dmanaged_register_mips.cc92 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { in operator <<()
97 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()

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