1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but because we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this earlier at some point
15 // in future.
16
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
20 // intstructions.
21 //
22 //
23 //===----------------------------------------------------------------------===//
24 #include "llvm/PassSupport.h"
25 #include "Hexagon.h"
26 #include "HexagonInstrInfo.h"
27 #include "HexagonMachineFunctionInfo.h"
28 #include "HexagonRegisterInfo.h"
29 #include "HexagonSubtarget.h"
30 #include "HexagonTargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include <map>
48 using namespace llvm;
49
50 #define DEBUG_TYPE "hexagon-nvj"
51
52 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
53
54 static cl::opt<int>
55 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
56 "Maximum number of predicated jumps to be converted to New Value Jump"));
57
58 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
59 cl::ZeroOrMore, cl::init(false),
60 cl::desc("Disable New Value Jumps"));
61
62 namespace llvm {
63 FunctionPass *createHexagonNewValueJump();
64 void initializeHexagonNewValueJumpPass(PassRegistry&);
65 }
66
67
68 namespace {
69 struct HexagonNewValueJump : public MachineFunctionPass {
70 const HexagonInstrInfo *QII;
71 const HexagonRegisterInfo *QRI;
72
73 public:
74 static char ID;
75
HexagonNewValueJump__anonbdbef39a0111::HexagonNewValueJump76 HexagonNewValueJump() : MachineFunctionPass(ID) {
77 initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
78 }
79
getAnalysisUsage__anonbdbef39a0111::HexagonNewValueJump80 void getAnalysisUsage(AnalysisUsage &AU) const override {
81 AU.addRequired<MachineBranchProbabilityInfo>();
82 MachineFunctionPass::getAnalysisUsage(AU);
83 }
84
getPassName__anonbdbef39a0111::HexagonNewValueJump85 const char *getPassName() const override {
86 return "Hexagon NewValueJump";
87 }
88
89 bool runOnMachineFunction(MachineFunction &Fn) override;
90
91 private:
92 /// \brief A handle to the branch probability pass.
93 const MachineBranchProbabilityInfo *MBPI;
94
95 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
96 };
97
98 } // end of anonymous namespace
99
100 char HexagonNewValueJump::ID = 0;
101
102 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
103 "Hexagon NewValueJump", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)104 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
105 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
106 "Hexagon NewValueJump", false, false)
107
108
109 // We have identified this II could be feeder to NVJ,
110 // verify that it can be.
111 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
112 const TargetRegisterInfo *TRI,
113 MachineBasicBlock::iterator II,
114 MachineBasicBlock::iterator end,
115 MachineBasicBlock::iterator skip,
116 MachineFunction &MF) {
117
118 // Predicated instruction can not be feeder to NVJ.
119 if (QII->isPredicated(II))
120 return false;
121
122 // Bail out if feederReg is a paired register (double regs in
123 // our case). One would think that we can check to see if a given
124 // register cmpReg1 or cmpReg2 is a sub register of feederReg
125 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
126 // before the callsite of this function
127 // But we can not as it comes in the following fashion.
128 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
129 // %R0<def> = KILL %R0, %D0<imp-use,kill>
130 // %P0<def> = CMPEQri %R0<kill>, 0
131 // Hence, we need to check if it's a KILL instruction.
132 if (II->getOpcode() == TargetOpcode::KILL)
133 return false;
134
135
136 // Make sure there there is no 'def' or 'use' of any of the uses of
137 // feeder insn between it's definition, this MI and jump, jmpInst
138 // skipping compare, cmpInst.
139 // Here's the example.
140 // r21=memub(r22+r24<<#0)
141 // p0 = cmp.eq(r21, #0)
142 // r4=memub(r3+r21<<#0)
143 // if (p0.new) jump:t .LBB29_45
144 // Without this check, it will be converted into
145 // r4=memub(r3+r21<<#0)
146 // r21=memub(r22+r24<<#0)
147 // p0 = cmp.eq(r21, #0)
148 // if (p0.new) jump:t .LBB29_45
149 // and result WAR hazards if converted to New Value Jump.
150
151 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
152 if (II->getOperand(i).isReg() &&
153 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
154 MachineBasicBlock::iterator localII = II;
155 ++localII;
156 unsigned Reg = II->getOperand(i).getReg();
157 for (MachineBasicBlock::iterator localBegin = localII;
158 localBegin != end; ++localBegin) {
159 if (localBegin == skip ) continue;
160 // Check for Subregisters too.
161 if (localBegin->modifiesRegister(Reg, TRI) ||
162 localBegin->readsRegister(Reg, TRI))
163 return false;
164 }
165 }
166 }
167 return true;
168 }
169
170 // These are the common checks that need to performed
171 // to determine if
172 // 1. compare instruction can be moved before jump.
173 // 2. feeder to the compare instruction can be moved before jump.
commonChecksToProhibitNewValueJump(bool afterRA,MachineBasicBlock::iterator MII)174 static bool commonChecksToProhibitNewValueJump(bool afterRA,
175 MachineBasicBlock::iterator MII) {
176
177 // If store in path, bail out.
178 if (MII->getDesc().mayStore())
179 return false;
180
181 // if call in path, bail out.
182 if (MII->getOpcode() == Hexagon::J2_call)
183 return false;
184
185 // if NVJ is running prior to RA, do the following checks.
186 if (!afterRA) {
187 // The following Target Opcode instructions are spurious
188 // to new value jump. If they are in the path, bail out.
189 // KILL sets kill flag on the opcode. It also sets up a
190 // single register, out of pair.
191 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
192 // %R0<def> = KILL %R0, %D0<imp-use,kill>
193 // %P0<def> = CMPEQri %R0<kill>, 0
194 // PHI can be anything after RA.
195 // COPY can remateriaze things in between feeder, compare and nvj.
196 if (MII->getOpcode() == TargetOpcode::KILL ||
197 MII->getOpcode() == TargetOpcode::PHI ||
198 MII->getOpcode() == TargetOpcode::COPY)
199 return false;
200
201 // The following pseudo Hexagon instructions sets "use" and "def"
202 // of registers by individual passes in the backend. At this time,
203 // we don't know the scope of usage and definitions of these
204 // instructions.
205 if (MII->getOpcode() == Hexagon::LDriw_pred ||
206 MII->getOpcode() == Hexagon::STriw_pred)
207 return false;
208 }
209
210 return true;
211 }
212
canCompareBeNewValueJump(const HexagonInstrInfo * QII,const TargetRegisterInfo * TRI,MachineBasicBlock::iterator II,unsigned pReg,bool secondReg,bool optLocation,MachineBasicBlock::iterator end,MachineFunction & MF)213 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
214 const TargetRegisterInfo *TRI,
215 MachineBasicBlock::iterator II,
216 unsigned pReg,
217 bool secondReg,
218 bool optLocation,
219 MachineBasicBlock::iterator end,
220 MachineFunction &MF) {
221
222 MachineInstr *MI = II;
223
224 // If the second operand of the compare is an imm, make sure it's in the
225 // range specified by the arch.
226 if (!secondReg) {
227 int64_t v = MI->getOperand(2).getImm();
228
229 if (!(isUInt<5>(v) ||
230 ((MI->getOpcode() == Hexagon::C2_cmpeqi ||
231 MI->getOpcode() == Hexagon::C2_cmpgti) &&
232 (v == -1))))
233 return false;
234 }
235
236 unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
237 cmpReg1 = MI->getOperand(1).getReg();
238
239 if (secondReg) {
240 cmpOp2 = MI->getOperand(2).getReg();
241
242 // Make sure that that second register is not from COPY
243 // At machine code level, we don't need this, but if we decide
244 // to move new value jump prior to RA, we would be needing this.
245 MachineRegisterInfo &MRI = MF.getRegInfo();
246 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
247 MachineInstr *def = MRI.getVRegDef(cmpOp2);
248 if (def->getOpcode() == TargetOpcode::COPY)
249 return false;
250 }
251 }
252
253 // Walk the instructions after the compare (predicate def) to the jump,
254 // and satisfy the following conditions.
255 ++II ;
256 for (MachineBasicBlock::iterator localII = II; localII != end;
257 ++localII) {
258
259 // Check 1.
260 // If "common" checks fail, bail out.
261 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
262 return false;
263
264 // Check 2.
265 // If there is a def or use of predicate (result of compare), bail out.
266 if (localII->modifiesRegister(pReg, TRI) ||
267 localII->readsRegister(pReg, TRI))
268 return false;
269
270 // Check 3.
271 // If there is a def of any of the use of the compare (operands of compare),
272 // bail out.
273 // Eg.
274 // p0 = cmp.eq(r2, r0)
275 // r2 = r4
276 // if (p0.new) jump:t .LBB28_3
277 if (localII->modifiesRegister(cmpReg1, TRI) ||
278 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
279 return false;
280 }
281 return true;
282 }
283
284
285 // Given a compare operator, return a matching New Value Jump compare operator.
286 // Make sure that MI here is included in isNewValueJumpCandidate.
getNewValueJumpOpcode(MachineInstr * MI,int reg,bool secondRegNewified,MachineBasicBlock * jmpTarget,const MachineBranchProbabilityInfo * MBPI)287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
288 bool secondRegNewified,
289 MachineBasicBlock *jmpTarget,
290 const MachineBranchProbabilityInfo
291 *MBPI) {
292 bool taken = false;
293 MachineBasicBlock *Src = MI->getParent();
294 const BranchProbability Prediction =
295 MBPI->getEdgeProbability(Src, jmpTarget);
296
297 if (Prediction >= BranchProbability(1,2))
298 taken = true;
299
300 switch (MI->getOpcode()) {
301 case Hexagon::C2_cmpeq:
302 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
303 : Hexagon::J4_cmpeq_t_jumpnv_nt;
304
305 case Hexagon::C2_cmpeqi: {
306 if (reg >= 0)
307 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
308 : Hexagon::J4_cmpeqi_t_jumpnv_nt;
309 else
310 return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
311 : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
312 }
313
314 case Hexagon::C2_cmpgt: {
315 if (secondRegNewified)
316 return taken ? Hexagon::J4_cmplt_t_jumpnv_t
317 : Hexagon::J4_cmplt_t_jumpnv_nt;
318 else
319 return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
320 : Hexagon::J4_cmpgt_t_jumpnv_nt;
321 }
322
323 case Hexagon::C2_cmpgti: {
324 if (reg >= 0)
325 return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
326 : Hexagon::J4_cmpgti_t_jumpnv_nt;
327 else
328 return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
329 : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
330 }
331
332 case Hexagon::C2_cmpgtu: {
333 if (secondRegNewified)
334 return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
335 : Hexagon::J4_cmpltu_t_jumpnv_nt;
336 else
337 return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
338 : Hexagon::J4_cmpgtu_t_jumpnv_nt;
339 }
340
341 case Hexagon::C2_cmpgtui:
342 return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
343 : Hexagon::J4_cmpgtui_t_jumpnv_nt;
344
345 case Hexagon::C4_cmpneq:
346 return taken ? Hexagon::J4_cmpeq_f_jumpnv_t
347 : Hexagon::J4_cmpeq_f_jumpnv_nt;
348
349 case Hexagon::C4_cmplte:
350 if (secondRegNewified)
351 return taken ? Hexagon::J4_cmplt_f_jumpnv_t
352 : Hexagon::J4_cmplt_f_jumpnv_nt;
353 return taken ? Hexagon::J4_cmpgt_f_jumpnv_t
354 : Hexagon::J4_cmpgt_f_jumpnv_nt;
355
356 case Hexagon::C4_cmplteu:
357 if (secondRegNewified)
358 return taken ? Hexagon::J4_cmpltu_f_jumpnv_t
359 : Hexagon::J4_cmpltu_f_jumpnv_nt;
360 return taken ? Hexagon::J4_cmpgtu_f_jumpnv_t
361 : Hexagon::J4_cmpgtu_f_jumpnv_nt;
362
363 default:
364 llvm_unreachable("Could not find matching New Value Jump instruction.");
365 }
366 // return *some value* to avoid compiler warning
367 return 0;
368 }
369
isNewValueJumpCandidate(const MachineInstr * MI) const370 bool HexagonNewValueJump::isNewValueJumpCandidate(const MachineInstr *MI)
371 const {
372 switch (MI->getOpcode()) {
373 case Hexagon::C2_cmpeq:
374 case Hexagon::C2_cmpeqi:
375 case Hexagon::C2_cmpgt:
376 case Hexagon::C2_cmpgti:
377 case Hexagon::C2_cmpgtu:
378 case Hexagon::C2_cmpgtui:
379 case Hexagon::C4_cmpneq:
380 case Hexagon::C4_cmplte:
381 case Hexagon::C4_cmplteu:
382 return true;
383
384 default:
385 return false;
386 }
387 }
388
389
runOnMachineFunction(MachineFunction & MF)390 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
391
392 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
393 << "********** Function: "
394 << MF.getName() << "\n");
395
396 // If we move NewValueJump before register allocation we'll need live variable
397 // analysis here too.
398
399 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
400 QRI = static_cast<const HexagonRegisterInfo *>(
401 MF.getSubtarget().getRegisterInfo());
402 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
403
404 if (DisableNewValueJumps) {
405 return false;
406 }
407
408 int nvjCount = DbgNVJCount;
409 int nvjGenerated = 0;
410
411 // Loop through all the bb's of the function
412 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
413 MBBb != MBBe; ++MBBb) {
414 MachineBasicBlock *MBB = &*MBBb;
415
416 DEBUG(dbgs() << "** dumping bb ** "
417 << MBB->getNumber() << "\n");
418 DEBUG(MBB->dump());
419 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
420 bool foundJump = false;
421 bool foundCompare = false;
422 bool invertPredicate = false;
423 unsigned predReg = 0; // predicate reg of the jump.
424 unsigned cmpReg1 = 0;
425 int cmpOp2 = 0;
426 bool MO1IsKill = false;
427 bool MO2IsKill = false;
428 MachineBasicBlock::iterator jmpPos;
429 MachineBasicBlock::iterator cmpPos;
430 MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr;
431 MachineBasicBlock *jmpTarget = nullptr;
432 bool afterRA = false;
433 bool isSecondOpReg = false;
434 bool isSecondOpNewified = false;
435 // Traverse the basic block - bottom up
436 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
437 MII != E;) {
438 MachineInstr *MI = --MII;
439 if (MI->isDebugValue()) {
440 continue;
441 }
442
443 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
444 break;
445
446 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
447
448 if (!foundJump &&
449 (MI->getOpcode() == Hexagon::J2_jumpt ||
450 MI->getOpcode() == Hexagon::J2_jumpf ||
451 MI->getOpcode() == Hexagon::J2_jumptnewpt ||
452 MI->getOpcode() == Hexagon::J2_jumptnew ||
453 MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
454 MI->getOpcode() == Hexagon::J2_jumpfnew)) {
455 // This is where you would insert your compare and
456 // instr that feeds compare
457 jmpPos = MII;
458 jmpInstr = MI;
459 predReg = MI->getOperand(0).getReg();
460 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
461
462 // If ifconverter had not messed up with the kill flags of the
463 // operands, the following check on the kill flag would suffice.
464 // if(!jmpInstr->getOperand(0).isKill()) break;
465
466 // This predicate register is live out out of BB
467 // this would only work if we can actually use Live
468 // variable analysis on phy regs - but LLVM does not
469 // provide LV analysis on phys regs.
470 //if(LVs.isLiveOut(predReg, *MBB)) break;
471
472 // Get all the successors of this block - which will always
473 // be 2. Check if the predicate register is live in in those
474 // successor. If yes, we can not delete the predicate -
475 // I am doing this only because LLVM does not provide LiveOut
476 // at the BB level.
477 bool predLive = false;
478 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
479 SIE = MBB->succ_end(); SI != SIE; ++SI) {
480 MachineBasicBlock* succMBB = *SI;
481 if (succMBB->isLiveIn(predReg)) {
482 predLive = true;
483 }
484 }
485 if (predLive)
486 break;
487
488 jmpTarget = MI->getOperand(1).getMBB();
489 foundJump = true;
490 if (MI->getOpcode() == Hexagon::J2_jumpf ||
491 MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
492 MI->getOpcode() == Hexagon::J2_jumpfnew) {
493 invertPredicate = true;
494 }
495 continue;
496 }
497
498 // No new value jump if there is a barrier. A barrier has to be in its
499 // own packet. A barrier has zero operands. We conservatively bail out
500 // here if we see any instruction with zero operands.
501 if (foundJump && MI->getNumOperands() == 0)
502 break;
503
504 if (foundJump &&
505 !foundCompare &&
506 MI->getOperand(0).isReg() &&
507 MI->getOperand(0).getReg() == predReg) {
508
509 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
510 if (isNewValueJumpCandidate(MI)) {
511
512 assert((MI->getDesc().isCompare()) &&
513 "Only compare instruction can be collapsed into New Value Jump");
514 isSecondOpReg = MI->getOperand(2).isReg();
515
516 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
517 afterRA, jmpPos, MF))
518 break;
519
520 cmpInstr = MI;
521 cmpPos = MII;
522 foundCompare = true;
523
524 // We need cmpReg1 and cmpOp2(imm or reg) while building
525 // new value jump instruction.
526 cmpReg1 = MI->getOperand(1).getReg();
527 if (MI->getOperand(1).isKill())
528 MO1IsKill = true;
529
530 if (isSecondOpReg) {
531 cmpOp2 = MI->getOperand(2).getReg();
532 if (MI->getOperand(2).isKill())
533 MO2IsKill = true;
534 } else
535 cmpOp2 = MI->getOperand(2).getImm();
536 continue;
537 }
538 }
539
540 if (foundCompare && foundJump) {
541
542 // If "common" checks fail, bail out on this BB.
543 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
544 break;
545
546 bool foundFeeder = false;
547 MachineBasicBlock::iterator feederPos = MII;
548 if (MI->getOperand(0).isReg() &&
549 MI->getOperand(0).isDef() &&
550 (MI->getOperand(0).getReg() == cmpReg1 ||
551 (isSecondOpReg &&
552 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
553
554 unsigned feederReg = MI->getOperand(0).getReg();
555
556 // First try to see if we can get the feeder from the first operand
557 // of the compare. If we can not, and if secondOpReg is true
558 // (second operand of the compare is also register), try that one.
559 // TODO: Try to come up with some heuristic to figure out which
560 // feeder would benefit.
561
562 if (feederReg == cmpReg1) {
563 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
564 if (!isSecondOpReg)
565 break;
566 else
567 continue;
568 } else
569 foundFeeder = true;
570 }
571
572 if (!foundFeeder &&
573 isSecondOpReg &&
574 feederReg == (unsigned) cmpOp2)
575 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
576 break;
577
578 if (isSecondOpReg) {
579 // In case of CMPLT, or CMPLTU, or EQ with the second register
580 // to newify, swap the operands.
581 if (cmpInstr->getOpcode() == Hexagon::C2_cmpeq &&
582 feederReg == (unsigned) cmpOp2) {
583 unsigned tmp = cmpReg1;
584 bool tmpIsKill = MO1IsKill;
585 cmpReg1 = cmpOp2;
586 MO1IsKill = MO2IsKill;
587 cmpOp2 = tmp;
588 MO2IsKill = tmpIsKill;
589 }
590
591 // Now we have swapped the operands, all we need to check is,
592 // if the second operand (after swap) is the feeder.
593 // And if it is, make a note.
594 if (feederReg == (unsigned)cmpOp2)
595 isSecondOpNewified = true;
596 }
597
598 // Now that we are moving feeder close the jump,
599 // make sure we are respecting the kill values of
600 // the operands of the feeder.
601
602 bool updatedIsKill = false;
603 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
604 MachineOperand &MO = MI->getOperand(i);
605 if (MO.isReg() && MO.isUse()) {
606 unsigned feederReg = MO.getReg();
607 for (MachineBasicBlock::iterator localII = feederPos,
608 end = jmpPos; localII != end; localII++) {
609 MachineInstr *localMI = localII;
610 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
611 MachineOperand &localMO = localMI->getOperand(j);
612 if (localMO.isReg() && localMO.isUse() &&
613 localMO.isKill() && feederReg == localMO.getReg()) {
614 // We found that there is kill of a use register
615 // Set up a kill flag on the register
616 localMO.setIsKill(false);
617 MO.setIsKill();
618 updatedIsKill = true;
619 break;
620 }
621 }
622 if (updatedIsKill) break;
623 }
624 }
625 if (updatedIsKill) break;
626 }
627
628 MBB->splice(jmpPos, MI->getParent(), MI);
629 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
630 DebugLoc dl = MI->getDebugLoc();
631 MachineInstr *NewMI;
632
633 assert((isNewValueJumpCandidate(cmpInstr)) &&
634 "This compare is not a New Value Jump candidate.");
635 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
636 isSecondOpNewified,
637 jmpTarget, MBPI);
638 if (invertPredicate)
639 opc = QII->getInvertedPredicatedOpcode(opc);
640
641 if (isSecondOpReg)
642 NewMI = BuildMI(*MBB, jmpPos, dl,
643 QII->get(opc))
644 .addReg(cmpReg1, getKillRegState(MO1IsKill))
645 .addReg(cmpOp2, getKillRegState(MO2IsKill))
646 .addMBB(jmpTarget);
647
648 else if ((cmpInstr->getOpcode() == Hexagon::C2_cmpeqi ||
649 cmpInstr->getOpcode() == Hexagon::C2_cmpgti) &&
650 cmpOp2 == -1 )
651 // Corresponding new-value compare jump instructions don't have the
652 // operand for -1 immediate value.
653 NewMI = BuildMI(*MBB, jmpPos, dl,
654 QII->get(opc))
655 .addReg(cmpReg1, getKillRegState(MO1IsKill))
656 .addMBB(jmpTarget);
657
658 else
659 NewMI = BuildMI(*MBB, jmpPos, dl,
660 QII->get(opc))
661 .addReg(cmpReg1, getKillRegState(MO1IsKill))
662 .addImm(cmpOp2)
663 .addMBB(jmpTarget);
664
665 assert(NewMI && "New Value Jump Instruction Not created!");
666 (void)NewMI;
667 if (cmpInstr->getOperand(0).isReg() &&
668 cmpInstr->getOperand(0).isKill())
669 cmpInstr->getOperand(0).setIsKill(false);
670 if (cmpInstr->getOperand(1).isReg() &&
671 cmpInstr->getOperand(1).isKill())
672 cmpInstr->getOperand(1).setIsKill(false);
673 cmpInstr->eraseFromParent();
674 jmpInstr->eraseFromParent();
675 ++nvjGenerated;
676 ++NumNVJGenerated;
677 break;
678 }
679 }
680 }
681 }
682
683 return true;
684
685 }
686
createHexagonNewValueJump()687 FunctionPass *llvm::createHexagonNewValueJump() {
688 return new HexagonNewValueJump();
689 }
690