1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 27 /***************************************************************************** 28 29 @File msvdx_vec_vp8_reg_io2.h 30 31 Title MSVDX Offsets 32 33 @Platform </b>\n 34 35 @Description </b>\n This file contains the MSVDX_VEC_VP8_REG_IO2_H Defintions. 36 37 ******************************************************************************/ 38 39 #if !defined (__MSVDX_VEC_VP8_REG_IO2_H__) 40 #define __MSVDX_VEC_VP8_REG_IO2_H__ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 47 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_OFFSET (0x0230) 48 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_STRIDE (4) 49 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_NO_ENTRIES (8) 50 51 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PARTITION_SIZE_N, VP8_FE_PARTITION_SIZE 52 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_VP8_FE_PARTITION_SIZE_MASK (0x0FFFFFFF) 53 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_VP8_FE_PARTITION_SIZE_LSBMASK (0x0FFFFFFF) 54 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_VP8_FE_PARTITION_SIZE_SHIFT (0) 55 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_VP8_FE_PARTITION_SIZE_SIGNED_FIELD IMG_FALSE 56 57 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_OFFSET (0x0200) 58 59 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_FRAME_TYPE 60 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_FRAME_TYPE_MASK (0x00000001) 61 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_FRAME_TYPE_LSBMASK (0x00000001) 62 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_FRAME_TYPE_SHIFT (0) 63 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_FRAME_TYPE_SIGNED_FIELD IMG_FALSE 64 65 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_NUM_PARTITION_MINUS1 66 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_NUM_PARTITION_MINUS1_MASK (0x0000000E) 67 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_NUM_PARTITION_MINUS1_LSBMASK (0x00000007) 68 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_NUM_PARTITION_MINUS1_SHIFT (1) 69 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_NUM_PARTITION_MINUS1_SIGNED_FIELD IMG_FALSE 70 71 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_SEG_ID_CTRL 72 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_SEG_ID_CTRL_MASK (0x00000030) 73 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_SEG_ID_CTRL_LSBMASK (0x00000003) 74 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_SEG_ID_CTRL_SHIFT (4) 75 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_SEG_ID_CTRL_SIGNED_FIELD IMG_FALSE 76 77 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC0, VP8_FE_UPDATE_SEGMENTATION_MAP 78 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_UPDATE_SEGMENTATION_MAP_MASK (0x00000100) 79 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_UPDATE_SEGMENTATION_MAP_LSBMASK (0x00000001) 80 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_UPDATE_SEGMENTATION_MAP_SHIFT (8) 81 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_UPDATE_SEGMENTATION_MAP_SIGNED_FIELD IMG_FALSE 82 83 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_OFFSET (0x0204) 84 85 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1, VP8_FE_PIC_HEIGHT_IN_MBS_LESS1 86 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_HEIGHT_IN_MBS_LESS1_MASK (0x0000FF00) 87 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_HEIGHT_IN_MBS_LESS1_LSBMASK (0x000000FF) 88 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_HEIGHT_IN_MBS_LESS1_SHIFT (8) 89 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_HEIGHT_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE 90 91 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC1, VP8_FE_PIC_WIDTH_IN_MBS_LESS1 92 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_WIDTH_IN_MBS_LESS1_MASK (0x000000FF) 93 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_WIDTH_IN_MBS_LESS1_LSBMASK (0x000000FF) 94 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_WIDTH_IN_MBS_LESS1_SHIFT (0) 95 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_WIDTH_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE 96 97 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_OFFSET (0x0208) 98 99 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_DECODE_PRED_NOT_COEFFS 100 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_DECODE_PRED_NOT_COEFFS_MASK (0x00000001) 101 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_DECODE_PRED_NOT_COEFFS_LSBMASK (0x00000001) 102 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_DECODE_PRED_NOT_COEFFS_SHIFT (0) 103 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_DECODE_PRED_NOT_COEFFS_SIGNED_FIELD IMG_FALSE 104 105 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_MB_NO_COEFF_SKIP 106 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_MB_NO_COEFF_SKIP_MASK (0x00000100) 107 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_MB_NO_COEFF_SKIP_LSBMASK (0x00000001) 108 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_MB_NO_COEFF_SKIP_SHIFT (8) 109 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_MB_NO_COEFF_SKIP_SIGNED_FIELD IMG_FALSE 110 111 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_SIGN_BIAS_FOR_GF 112 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_GF_MASK (0x00010000) 113 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_GF_LSBMASK (0x00000001) 114 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_GF_SHIFT (16) 115 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_GF_SIGNED_FIELD IMG_FALSE 116 117 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC2, VP8_FE_SIGN_BIAS_FOR_ALTREF 118 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_ALTREF_MASK (0x01000000) 119 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_ALTREF_LSBMASK (0x00000001) 120 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_ALTREF_SHIFT (24) 121 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_ALTREF_SIGNED_FIELD IMG_FALSE 122 123 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_OFFSET (0x020C) 124 125 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB0 126 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB0_MASK (0x000000FF) 127 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB0_LSBMASK (0x000000FF) 128 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB0_SHIFT (0) 129 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB0_SIGNED_FIELD IMG_FALSE 130 131 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB1 132 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB1_MASK (0x0000FF00) 133 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB1_LSBMASK (0x000000FF) 134 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB1_SHIFT (8) 135 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB1_SIGNED_FIELD IMG_FALSE 136 137 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_SEGMENT_PROBS, VP8_FE_SEGMENT_ID_PROB2 138 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB2_MASK (0x00FF0000) 139 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB2_LSBMASK (0x000000FF) 140 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB2_SHIFT (16) 141 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_SEGMENT_PROBS_VP8_FE_SEGMENT_ID_PROB2_SIGNED_FIELD IMG_FALSE 142 143 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_OFFSET (0x0210) 144 145 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_SKIP_PROB 146 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_SKIP_PROB_MASK (0x000000FF) 147 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_SKIP_PROB_LSBMASK (0x000000FF) 148 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_SKIP_PROB_SHIFT (0) 149 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_SKIP_PROB_SIGNED_FIELD IMG_FALSE 150 151 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_INTRA_MB_PROB 152 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_INTRA_MB_PROB_MASK (0x0000FF00) 153 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_INTRA_MB_PROB_LSBMASK (0x000000FF) 154 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_INTRA_MB_PROB_SHIFT (8) 155 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_INTRA_MB_PROB_SIGNED_FIELD IMG_FALSE 156 157 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_LAST_FRAME_PROB 158 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_LAST_FRAME_PROB_MASK (0x00FF0000) 159 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_LAST_FRAME_PROB_LSBMASK (0x000000FF) 160 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_LAST_FRAME_PROB_SHIFT (16) 161 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_LAST_FRAME_PROB_SIGNED_FIELD IMG_FALSE 162 163 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_MB_FLAGS_PROBS, VP8_FE_GOLDEN_FRAME_PROB 164 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_GOLDEN_FRAME_PROB_MASK (0xFF000000) 165 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_GOLDEN_FRAME_PROB_LSBMASK (0x000000FF) 166 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_GOLDEN_FRAME_PROB_SHIFT (24) 167 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_MB_FLAGS_PROBS_VP8_FE_GOLDEN_FRAME_PROB_SIGNED_FIELD IMG_FALSE 168 169 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS_OFFSET (0x0214) 170 171 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS, VP8_FE_SEG_ID_BASE_ADDRESS 172 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS_VP8_FE_SEG_ID_BASE_ADDRESS_MASK (0xFFFFF000) 173 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS_VP8_FE_SEG_ID_BASE_ADDRESS_LSBMASK (0x000FFFFF) 174 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS_VP8_FE_SEG_ID_BASE_ADDRESS_SHIFT (12) 175 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_SEG_ID_BASE_ADDRESS_VP8_FE_SEG_ID_BASE_ADDRESS_SIGNED_FIELD IMG_FALSE 176 177 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS_OFFSET (0x0220) 178 179 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS, VP8_FE_PIC_MB_BASE_ADDRESS 180 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS_VP8_FE_PIC_MB_BASE_ADDRESS_MASK (0xFFFFFFFF) 181 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS_VP8_FE_PIC_MB_BASE_ADDRESS_LSBMASK (0xFFFFFFFF) 182 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS_VP8_FE_PIC_MB_BASE_ADDRESS_SHIFT (0) 183 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC_MB_FLAGS_BASE_ADDRESS_VP8_FE_PIC_MB_BASE_ADDRESS_SIGNED_FIELD IMG_FALSE 184 185 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_DCT_BASE_ADDRESS_OFFSET (0x0224) 186 187 // MSVDX_VEC_VP8, CR_VEC_VP8_FE_DCT_BASE_ADDRESS, VP8_FE_DCT_BASE_ADDRESS 188 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_DCT_BASE_ADDRESS_VP8_FE_DCT_BASE_ADDRESS_MASK (0xFFFFFFFF) 189 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_DCT_BASE_ADDRESS_VP8_FE_DCT_BASE_ADDRESS_LSBMASK (0xFFFFFFFF) 190 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_DCT_BASE_ADDRESS_VP8_FE_DCT_BASE_ADDRESS_SHIFT (0) 191 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_DCT_BASE_ADDRESS_VP8_FE_DCT_BASE_ADDRESS_SIGNED_FIELD IMG_FALSE 192 193 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC0_OFFSET (0x0250) 194 195 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC0, VP8_BE_FRAME_TYPE 196 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC0_VP8_BE_FRAME_TYPE_MASK (0x00000001) 197 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC0_VP8_BE_FRAME_TYPE_LSBMASK (0x00000001) 198 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC0_VP8_BE_FRAME_TYPE_SHIFT (0) 199 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC0_VP8_BE_FRAME_TYPE_SIGNED_FIELD IMG_FALSE 200 201 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_OFFSET (0x0254) 202 203 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC1, VP8_BE_PIC_HEIGHT_IN_MBS_LESS1 204 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_HEIGHT_IN_MBS_LESS1_MASK (0x0000FF00) 205 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_HEIGHT_IN_MBS_LESS1_LSBMASK (0x000000FF) 206 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_HEIGHT_IN_MBS_LESS1_SHIFT (8) 207 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_HEIGHT_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE 208 209 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC1, VP8_BE_PIC_WIDTH_IN_MBS_LESS1 210 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_WIDTH_IN_MBS_LESS1_MASK (0x000000FF) 211 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_WIDTH_IN_MBS_LESS1_LSBMASK (0x000000FF) 212 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_WIDTH_IN_MBS_LESS1_SHIFT (0) 213 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC1_VP8_BE_PIC_WIDTH_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE 214 215 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_OFFSET (0x0258) 216 217 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2, VP8_BE_DECODE_PRED_NOT_COEFFS 218 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_DECODE_PRED_NOT_COEFFS_MASK (0x00000001) 219 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_DECODE_PRED_NOT_COEFFS_LSBMASK (0x00000001) 220 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_DECODE_PRED_NOT_COEFFS_SHIFT (0) 221 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_DECODE_PRED_NOT_COEFFS_SIGNED_FIELD IMG_FALSE 222 223 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_PIC2, VP8_BE_USE_STORED_SEGMENT_MAP 224 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_USE_STORED_SEGMENT_MAP_MASK (0x00000100) 225 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_USE_STORED_SEGMENT_MAP_LSBMASK (0x00000001) 226 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_USE_STORED_SEGMENT_MAP_SHIFT (8) 227 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_PIC2_VP8_BE_USE_STORED_SEGMENT_MAP_SIGNED_FIELD IMG_FALSE 228 229 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_OFFSET (0x02E4) 230 231 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG0_DEFAULT 232 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG0_DEFAULT_MASK (0x000000FF) 233 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG0_DEFAULT_LSBMASK (0x000000FF) 234 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG0_DEFAULT_SHIFT (0) 235 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG0_DEFAULT_SIGNED_FIELD IMG_FALSE 236 237 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG1 238 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG1_MASK (0x0000FF00) 239 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG1_LSBMASK (0x000000FF) 240 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG1_SHIFT (8) 241 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG1_SIGNED_FIELD IMG_FALSE 242 243 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG2 244 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG2_MASK (0x00FF0000) 245 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG2_LSBMASK (0x000000FF) 246 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG2_SHIFT (16) 247 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG2_SIGNED_FIELD IMG_FALSE 248 249 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QINDEXMAP, VP8_BE_QINDEX_SEG3 250 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG3_MASK (0xFF000000) 251 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG3_LSBMASK (0x000000FF) 252 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG3_SHIFT (24) 253 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QINDEXMAP_VP8_BE_QINDEX_SEG3_SIGNED_FIELD IMG_FALSE 254 255 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_OFFSET (0x02E8) 256 257 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_YDC_DELTA 258 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_YDC_DELTA_MASK (0x1F000000) 259 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_YDC_DELTA_LSBMASK (0x0000001F) 260 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_YDC_DELTA_SHIFT (24) 261 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_YDC_DELTA_SIGNED_FIELD IMG_FALSE 262 263 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_Y2DC_DELTA 264 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2DC_DELTA_MASK (0x001F0000) 265 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2DC_DELTA_LSBMASK (0x0000001F) 266 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2DC_DELTA_SHIFT (16) 267 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2DC_DELTA_SIGNED_FIELD IMG_FALSE 268 269 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_Y2AC_DELTA 270 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2AC_DELTA_MASK (0x00007C00) 271 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2AC_DELTA_LSBMASK (0x0000001F) 272 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2AC_DELTA_SHIFT (10) 273 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_Y2AC_DELTA_SIGNED_FIELD IMG_FALSE 274 275 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_UVDC_DELTA 276 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVDC_DELTA_MASK (0x000003E0) 277 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVDC_DELTA_LSBMASK (0x0000001F) 278 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVDC_DELTA_SHIFT (5) 279 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVDC_DELTA_SIGNED_FIELD IMG_FALSE 280 281 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_QDELTAS, VP8_BE_UVAC_DELTA 282 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVAC_DELTA_MASK (0x0000001F) 283 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVAC_DELTA_LSBMASK (0x0000001F) 284 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVAC_DELTA_SHIFT (0) 285 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_QDELTAS_VP8_BE_UVAC_DELTA_SIGNED_FIELD IMG_FALSE 286 287 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_VLR_BASE_ADDR_OFFSET (0x02F0) 288 289 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_VLR_BASE_ADDR, VP8_BE_DP_BUFFER_VLR_BASE_ADDR 290 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_VLR_BASE_ADDR_VP8_BE_DP_BUFFER_VLR_BASE_ADDR_MASK (0x00000FFF) 291 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_VLR_BASE_ADDR_VP8_BE_DP_BUFFER_VLR_BASE_ADDR_LSBMASK (0x00000FFF) 292 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_VLR_BASE_ADDR_VP8_BE_DP_BUFFER_VLR_BASE_ADDR_SHIFT (0) 293 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_VLR_BASE_ADDR_VP8_BE_DP_BUFFER_VLR_BASE_ADDR_SIGNED_FIELD IMG_FALSE 294 295 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC_OFFSET (0x02EC) 296 297 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC, VP8_BE_BASE_ADDR_1STPART_PIC 298 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC_VP8_BE_BASE_ADDR_1STPART_PIC_MASK (0xFFFFF000) 299 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC_VP8_BE_BASE_ADDR_1STPART_PIC_LSBMASK (0x000FFFFF) 300 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC_VP8_BE_BASE_ADDR_1STPART_PIC_SHIFT (12) 301 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_1STPART_PIC_VP8_BE_BASE_ADDR_1STPART_PIC_SIGNED_FIELD IMG_FALSE 302 303 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_CURR_OFFSET (0x02F8) 304 305 // MSVDX_VEC_VP8, CR_VEC_VP8_BE_BASE_ADDR_CURR, VP8_BE_BASE_ADDR_CUR_PIC 306 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_CURR_VP8_BE_BASE_ADDR_CUR_PIC_MASK (0xFFFFF000) 307 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_CURR_VP8_BE_BASE_ADDR_CUR_PIC_LSBMASK (0x000FFFFF) 308 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_CURR_VP8_BE_BASE_ADDR_CUR_PIC_SHIFT (12) 309 #define MSVDX_VEC_VP8_CR_VEC_VP8_BE_BASE_ADDR_CURR_VP8_BE_BASE_ADDR_CUR_PIC_SIGNED_FIELD IMG_FALSE 310 311 312 313 #ifdef __cplusplus 314 } 315 #endif 316 317 #endif /* __MSVDX_VEC_VP8_REG_IO2_H__ */ 318