Searched refs:AllocateReg (Results 1 – 10 of 10) sorted by relevance
34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()83 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()102 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()256 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()267 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
1982 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()1989 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()2002 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()2019 State->AllocateReg(GPRArgRegs); in HandleByVal()
341 unsigned AllocateReg(unsigned Reg) { in AllocateReg() function348 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() function358 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function399 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
645 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()646 CCInfo.AllocateReg(AMDGPU::VGPR1); in LowerFormalArguments()658 CCInfo.AllocateReg(PrivateSegmentBufferReg); in LowerFormalArguments()664 CCInfo.AllocateReg(DispatchPtrReg); in LowerFormalArguments()670 CCInfo.AllocateReg(InputPtrReg); in LowerFormalArguments()767 CCInfo.AllocateReg(Reg); in LowerFormalArguments()774 CCInfo.AllocateReg(Reg); in LowerFormalArguments()780 CCInfo.AllocateReg(Reg); in LowerFormalArguments()786 CCInfo.AllocateReg(Reg); in LowerFormalArguments()795 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg); in LowerFormalArguments()[all …]
128 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
280 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Hexagon32()294 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in CC_Hexagon64()305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { in CC_Hexagon64()339 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()350 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()362 if (unsigned Reg = State.AllocateReg(VecLstD)) { in CC_HexagonVector()373 if (unsigned Reg = State.AllocateReg(VecLstS)) { in CC_HexagonVector()448 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { in RetCC_Hexagon32()463 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { in RetCC_Hexagon64()484 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { in RetCC_HexagonVector()[all …]
2417 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()2421 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()2426 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()2428 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()2429 State.AllocateReg(IntRegs); in CC_MipsO32()2434 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()2436 State.AllocateReg(IntRegs); in CC_MipsO32()2438 Reg = State.AllocateReg(F64Regs); in CC_MipsO32()2440 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()2442 State.AllocateReg(IntRegs); in CC_MipsO32()[all …]
60 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()71 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()89 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()95 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
327 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
2591 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()2617 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()