| /external/llvm/test/CodeGen/X86/ |
| D | 2010-03-05-ConstantFoldCFG.ll | 3 ; When BRCOND is constant-folded to BR, make sure that PHI nodes don't get
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 565 BRCOND, enumerator
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 133 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in SITargetLowering()
955 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
1026 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, in LowerBRCOND() argument
1029 SDLoc DL(BRCOND); in LowerBRCOND()
1031 SDNode *Intr = BRCOND.getOperand(1).getNode(); in LowerBRCOND()
1032 SDValue Target = BRCOND.getOperand(2); in LowerBRCOND()
1045 BR = findUser(BRCOND, ISD::BR); in LowerBRCOND()
1056 Ops.push_back(BRCOND.getOperand(0)); in LowerBRCOND()
1069 BRCOND.getOperand(2) in LowerBRCOND()
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| D | R600ISelLowering.cpp | 72 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in R600TargetLowering()
611 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
215 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in InitAMDILLowering()
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| D | AMDGPUISelLowering.cpp | 93 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 42 BRCOND, // Conditional branch instruction; "b.cond". enumerator
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| D | AArch64ISelLowering.cpp | 118 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AArch64TargetLowering()
842 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND"; in getTargetNodeName()
3620 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
3685 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
3698 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); in LowerBR_CC()
3701 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, in LowerBR_CC()
9646 case AArch64ISD::BRCOND: in PerformDAGCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 47 BRCOND, // Conditional branch. enumerator
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| D | ARMISelLowering.cpp | 912 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in ARMTargetLowering()
1110 case ARMISD::BRCOND: return "ARMISD::BRCOND"; in getTargetNodeName()
3776 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in OptimizeVFPBrcond()
3820 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, in LowerBR_CC()
3842 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
3846 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops); in LowerBR_CC()
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| D | ARMISelDAGToDAG.cpp | 2731 case ARMISD::BRCOND: { in Select()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 123 BRCOND, enumerator
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| D | X86ISelLowering.cpp | 295 setOperationAction(ISD::BRCOND , MVT::Other, Custom); in X86TargetLowering()
13752 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC && in hasNonFlagsUse()
15585 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), in LowerBRCOND()
15616 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), in LowerBRCOND()
15661 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), in LowerBRCOND()
15691 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), in LowerBRCOND()
15724 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), in LowerBRCOND()
20098 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
20442 case X86ISD::BRCOND: return "X86ISD::BRCOND"; in getTargetNodeName()
25146 case ISD::BRCOND: in CMPEQCombine()
[all …]
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 281 case ISD::BRCOND: return "brcond"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 1822 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSwitchCase()
1886 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitJumpTableHeader()
1952 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, in visitSPDescriptorParent()
2027 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl, in visitBitTestHeader()
2087 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl, in visitBitTestCase()
8166 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond, in lowerWorkItem()
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| D | DAGCombiner.cpp | 1431 case ISD::BRCOND: return visitBRCOND(N); in visit()
4902 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
4907 if (Use->getOpcode() == ISD::BRCOND) in visitSRL()
9387 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, DL, in visitBRCOND()
9427 return DAG.getNode(ISD::BRCOND, SDLoc(N), in visitBRCOND()
9456 return DAG.getNode(ISD::BRCOND, SDLoc(N), in visitBRCOND()
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| D | LegalizeIntegerTypes.cpp | 880 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; in PromoteIntegerOperand()
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| D | LegalizeDAG.cpp | 3741 case ISD::BRCOND: in ExpandNode()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 106 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 107 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in MSP430TargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 460 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 284 setOperationAction(ISD::BRCOND, MVT::Other, Custom); in MipsTargetLowering()
868 case ISD::BRCOND: return lowerBRCOND(Op, DAG); in LowerOperation()
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| D | MipsSEISelLowering.cpp | 188 setOperationAction(ISD::BRCOND, MVT::Other, Legal); in MipsSETargetLowering()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 247 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
849 setTargetDAGCombine(ISD::BRCOND); in PPCTargetLowering()
10600 case ISD::BRCOND: { in PerformDAGCombine()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1549 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
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