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Searched refs:BuildMI (Results 1 – 25 of 163) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp146 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
168 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
180 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
189 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
192 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
207 BuildMI(MBB, MBB.getFirstNonPHI(), DL, in Else()
211 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
227 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in Break()
242 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in IfBreak()
[all …]
DSIInstrInfo.cpp368 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
375 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
380 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32)) in copyPhysReg()
389 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
411 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
460 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in copyPhysReg()
565 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
577 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) in storeRegToStackSlot()
587 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
651 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
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/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
110 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
150 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
153 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
191 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
194 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
228 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
231 MachineInstr *NewMI = BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
254 BuildMI(*MBB, MII, MI->getDebugLoc(), in runOnMachineFunction()
257 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_add), in runOnMachineFunction()
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DHexagonSplitDouble.cpp565 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc)); in createHalfInstr()
620 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first) in splitMemRef()
623 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second) in splitMemRef()
629 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
633 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
647 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR) in splitMemRef()
690 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first) in splitImmediate()
692 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitImmediate()
711 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitCombine()
714 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
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DHexagonCopyToCombine.cpp551 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
558 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
567 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
574 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
583 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
589 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
597 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
604 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
615 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
623 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
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/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
297 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
316 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
319 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
320 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
329 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
334 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
335 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
[all …]
DMipsSEFrameLowering.cpp161 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
175 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
199 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
201 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
221 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
223 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
254 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
255 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
257 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
258 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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DMipsSEInstrInfo.cpp107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) in copyPhysReg()
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
229 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
232 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); in storeRegToStack()
235 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); in storeRegToStack()
238 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); in storeRegToStack()
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
300 BuildMI(MBB, I, DL, get(Opc), DestReg) in loadRegFromStack()
320 BuildMI(MBB, I, DL, get(Opc), Reg) in loadRegFromStack()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) in AnalyzeBranch()
207 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) in AnalyzeBranch()
240 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in InsertBranch()
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in InsertBranch()
254 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in InsertBranch()
297 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
305 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
309 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
320 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
[all …]
DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
163 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
168 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
176 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp270 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
275 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
294 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
347 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
356 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
400 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
581 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
584 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInline()
589 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX); in emitStackProbeInline()
594 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h233 inline MachineInstrBuilder BuildMI(MachineFunction &MF, in BuildMI() function
241 inline MachineInstrBuilder BuildMI(MachineFunction &MF, in BuildMI() function
252 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
263 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
274 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
281 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
285 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
291 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
301 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
311 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
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/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
752 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
762 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg); in emitPrologue()
769 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
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DPPCRegisterInfo.cpp359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
414 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
420 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
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DPPCBranchSelector.cpp197 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
201 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
204 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
206 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
212 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2); in runOnMachineFunction()
218 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest); in runOnMachineFunction()
DPPCFastISel.cpp430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8), in PPCSimplifyAddress()
537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
545 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
569 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
670 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
681 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
702 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in PPCEmitStore()
776 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC)) in SelectBranch()
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
[all …]
DPPCInstrInfo.cpp380 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) in commuteInstructionImpl()
434 BuildMI(MBB, MI, DL, get(Opcode)); in insertNoop()
651 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in InsertBranch()
653 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch()
657 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
659 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
661 BuildMI(&MBB, DL, get(PPC::BCC)) in InsertBranch()
668 BuildMI(&MBB, DL, get(Cond[0].getImm() ? in InsertBranch()
672 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
674 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB); in InsertBranch()
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFrameLowering.cpp76 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), SPReg) in adjustStackPointer()
84 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32), SPReg) in adjustStackPointer()
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
92 BuildMI(MBB, InsertPt, DL, in adjustStackPointer()
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
102 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32) in adjustStackPointer()
159 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
162 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), WebAssembly::SP32) in emitEpilogue()
166 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
170 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32) in emitEpilogue()
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp218 BuildMI(MBB, std::next(Info.I), dl, in emitDefCFAOffsets()
258 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
263 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg) in emitAligningInstructions()
272 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
276 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg) in emitAligningInstructions()
284 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg) in emitAligningInstructions()
453 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4) in emitPrologue()
457 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4) in emitPrologue()
466 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
474 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12) in emitPrologue()
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DThumb1FrameLowering.cpp127 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
139 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
202 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
230 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) in emitPrologue()
248 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
255 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
273 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
297 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr) in emitPrologue()
370 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), in emitEpilogue()
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/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp68 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
72 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
100 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
137 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
158 BuildMI(MBB, MBBI, DL, in emitEpilogue()
162 BuildMI(MBB, MBBI, DL, in emitEpilogue()
172 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
201 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
222 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); in restoreCalleeSavedRegisters()
249 New = BuildMI(MF, Old->getDebugLoc(), in eliminateCallFramePseudoInstr()
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/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
177 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0); in InsertSPConstInst()
[all …]
DXCoreInstrInfo.cpp289 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); in InsertBranch()
293 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
302 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in InsertBranch()
304 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); in InsertBranch()
340 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
347 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
352 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) in copyPhysReg()
375 BuildMI(MBB, I, DL, get(XCore::STWFI)) in storeRegToStackSlot()
397 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()
438 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg) in loadImmediate()
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/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV)) in EmitInstrWithCustomInserter()
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY)) in EmitInstrWithCustomInserter()
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32), in EmitInstrWithCustomInserter()
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr) in EmitInstrWithCustomInserter()
138 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) in EmitInstrWithCustomInserter()
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0) in EmitInstrWithCustomInserter()
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1) in EmitInstrWithCustomInserter()
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G)) in EmitInstrWithCustomInserter()
[all …]
DSIISelLowering.cpp82 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
97 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
112 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) in EmitInstrWithCustomInserter()
145 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WAITCNT)) in AppendS_WAITCNT()
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP()
164 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp) in LowerSI_INTERP()
170 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32)) in LowerSI_INTERP()
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0) in LowerSI_INTERP_CONST()
194 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32)) in LowerSI_INTERP_CONST()
207 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMPX_LE_F32_e32), in LowerSI_KIL()
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