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Searched refs:CMOV (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/CodeGen/X86/
Datomic32.ll1 …lc < %s -O0 -march=x86-64 -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefix=WITH-CMOV
2 …: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefix=WITH-CMOV
8 ; WITH-CMOV-LABEL: atomic_fetch_add32:
12 ; WITH-CMOV: lock
13 ; WITH-CMOV: incl
15 ; WITH-CMOV: lock
16 ; WITH-CMOV: addl $3
18 ; WITH-CMOV: lock
19 ; WITH-CMOV: xaddl
21 ; WITH-CMOV: lock
[all …]
Dcmovcmov.ll1 …verbose=false -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
12 ; CMOV-NEXT: ucomiss %xmm1, %xmm0
13 ; CMOV-NEXT: cmovnel %esi, %edi
14 ; CMOV-NEXT: cmovpl %esi, %edi
15 ; CMOV-NEXT: movl %edi, %eax
16 ; CMOV-NEXT: retq
39 ; CMOV-NEXT: ucomiss %xmm1, %xmm0
40 ; CMOV-NEXT: cmovneq %rsi, %rdi
41 ; CMOV-NEXT: cmovpq %rsi, %rdi
42 ; CMOV-NEXT: movq %rdi, %rax
[all …]
Dpseudo_cmov_lower.ll4 ; for lowering the CMOV pseudos that get created for this IR.
18 ; for lowering the CMOV pseudos that get created for this IR. This makes
35 ; for lowering the CMOV pseudos that get created for this IR.
51 ; for lowering the CMOV pseudos that get created for this IR.
67 ; for lowering the CMOV pseudos that get created for this IR.
81 ; for lowering the CMOV pseudos that get created for this IR.
95 ; for lowering the CMOV pseudos that get created for this IR.
109 ; for lowering the CMOV pseudos that get created for this IR.
123 ; for lowering the CMOV pseudos that get created for this IR. This combines
214 ; for lowering the CMOV pseudos that get created for this IR.
Dpseudo_cmov_lower2.ll4 ; for lowering the CMOV pseudos that get created for this IR. The tricky part
25 ; for lowering the CMOV pseudos that get created for this IR. The tricky part
46 ; for lowering the CMOV pseudos that get created for this IR. The tricky part
72 ; for lowering the CMOV pseudos that get created for this IR. The tricky part
Dpseudo_cmov_lower1.ll5 ; for lowering the CMOV pseudos that get created for this IR.
23 ; for lowering the CMOV pseudos that get created for this IR.
D2010-09-30-CMOV-JumpTable-PHI.ll6 ; -mcpu=i386 doesn't have CMOV.'
Dcmpxchg-clobber-flags.ll127 ; This one is an interesting case because CMOV doesn't have a chain
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect.ll4 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
5 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
7 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
8 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
10 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
11 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
13 ; RUN: -check-prefix=ALL -check-prefix=CMOV \
14 ; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
20 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
22 ; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
[all …]
/external/llvm/test/CodeGen/Mips/
Dcmov.ll1 …h=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
2 …h=mips -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
3 …h=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
5 …h=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
6 …h=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
14 ; 32-CMOV-DAG: lw $[[R0:[0-9]+]], %got(i3)
15 ; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
17 ; 32-CMOV-DAG: lw $2, 0($[[R0]])
26 ; 64-CMOV-DAG: ldr $[[R0:[0-9]+]]
[all …]
Dzeroreg.ll1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
4 ; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
5 ; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
6 ; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
15 ; 32-CMOV: lw $2, 0(${{[0-9]+}})
16 ; 32-CMOV: movn $2, $zero, $4
21 ; 64-CMOV: lw $2, 0(${{[0-9]+}})
22 ; 64-CMOV: movn $2, $zero, $4
37 ; 32-CMOV: lw $2, 0(${{[0-9]+}})
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCMovSetCC.td16 // CMOV instructions.
17 multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
64 defm CMOVO : CMOV<0x40, "cmovo" , X86_COND_O>;
65 defm CMOVNO : CMOV<0x41, "cmovno", X86_COND_NO>;
66 defm CMOVB : CMOV<0x42, "cmovb" , X86_COND_B>;
67 defm CMOVAE : CMOV<0x43, "cmovae", X86_COND_AE>;
68 defm CMOVE : CMOV<0x44, "cmove" , X86_COND_E>;
69 defm CMOVNE : CMOV<0x45, "cmovne", X86_COND_NE>;
70 defm CMOVBE : CMOV<0x46, "cmovbe", X86_COND_BE>;
71 defm CMOVA : CMOV<0x47, "cmova" , X86_COND_A>;
[all …]
DX86ISelLowering.h117 CMOV, enumerator
DX86SchedHaswell.td442 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
445 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
1140 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
DX86InstrCompiler.td508 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
511 def CMOV#NAME : I<0, Pseudo,
1212 N->getOpcode() != X86ISD::CMOV;
DX86ISelLowering.cpp12500 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0); in LowerShiftParts()
12501 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1); in LowerShiftParts()
12503 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0); in LowerShiftParts()
12504 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1); in LowerShiftParts()
15076 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond); in LowerSELECT()
15085 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops); in LowerSELECT()
17224 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, in LowerINTRINSIC_W_CHAIN()
17835 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops); in LowerCTLZ()
17919 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops); in LowerCTTZ()
20441 case X86ISD::CMOV: return "X86ISD::CMOV"; in getTargetNodeName()
[all …]
DX86InstrInfo.td133 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
/external/llvm/lib/Target/ARM/
DARMISelLowering.h62 CMOV, // ARM conditional move instructions. enumerator
DARMISelLowering.cpp1124 case ARMISD::CMOV: return "ARMISD::CMOV"; in getTargetNodeName()
3442 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal, in LowerXALUO()
3478 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { in LowerSELECT()
3582 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow, in getCMOV()
3584 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh, in getCMOV()
3589 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, in getCMOV()
4281 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, in LowerShiftRightParts()
4315 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
10390 if (Op.getOpcode() == ARMISD::CMOV) { in computeKnownBits()
10403 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const { in PerformCMOVToBFICombine() argument
[all …]
DARMInstrFormats.td158 // Selectable predicate operand for CMOV instructions. We can't use a normal
DARMInstrInfo.td128 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
/external/regex-re2/benchlog/
Dbenchlog.mini70 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFS…
Dbenchlog.wreck90 machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH…
/external/clang/lib/CodeGen/
DCGBuiltin.cpp6173 CMOV = 0, in EmitX86BuiltinExpr() enumerator
6195 .Case("cmov", X86Features::CMOV) in EmitX86BuiltinExpr()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td5201 // FIXME: X86 also checks for CMOV here. Do we need something similar?