Searched refs:CopyToReg (Results 1 – 18 of 18) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | copy-to-reg.ll | 4 ; Test that CopyToReg instructions don't have non-register operands prior
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 113 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
196 if (User->getOpcode() == ISD::CopyToReg && in getDstOfOnlyCopyToRegUse()
245 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
477 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
851 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
895 case ISD::CopyToReg: { in EmitSpecialNode()
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| D | ResourcePriorityQueue.cpp | 89 case ISD::CopyToReg: break; in numberRCValPredInSU()
126 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
457 case ISD::CopyToReg: in SUSchedulingCost()
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| D | ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
409 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
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| D | ScheduleDAGRRList.cpp | 681 case ISD::CopyToReg: in EmitNode()
1903 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2123 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2211 I->getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2262 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2594 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2839 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
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| D | SelectionDAGDumper.cpp | 143 case ISD::CopyToReg: return "CopyToReg"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 64 case ISD::CopyToReg: in SoftenFloatResult()
783 case ISD::CopyToReg: in CanSkipSoftenFloatOperand()
798 case ISD::CopyToReg: in CanSkipSoftenFloatOperand()
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| D | SelectionDAGISel.cpp | 690 if (N->getOpcode() != ISD::CopyToReg) in ComputeLiveOutVRegInfo()
2127 UserOpcode == ISD::CopyToReg || in WalkChainUsers()
2618 case ISD::CopyToReg: in SelectCodeCommon()
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| D | DAGCombiner.cpp | 5820 if (User->getOpcode() == ISD::CopyToReg) in ExtendUsesToFormExtLoad()
5829 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { in ExtendUsesToFormExtLoad()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 165 CopyToReg, enumerator
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| D | SelectionDAG.h | 524 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
535 return getNode(ISD::CopyToReg, dl, VTs,
544 return getNode(ISD::CopyToReg, dl, VTs,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1080 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); in LowerBRCOND() local
1081 if (!CopyToReg) in LowerBRCOND()
1086 CopyToReg->getOperand(1), in LowerBRCOND()
1090 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0)); in LowerBRCOND()
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| D | AMDGPUISelDAGToDAG.cpp | 496 case ISD::CopyToReg: { in Select()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2018 if (UI->getOpcode() != ISD::CopyToReg) in hasNoSignedComparisonUses()
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| D | X86ISelLowering.cpp | 2328 if (Copy->getOpcode() == ISD::CopyToReg) { in isUsedByReturnOnly()
13853 if (UI->getOpcode() != ISD::CopyToReg && in EmitTest()
25150 case ISD::CopyToReg: in CMPEQCombine()
27805 if (UI->getOpcode() != ISD::CopyToReg) in IsDesirableToPromoteOp()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 440 if (Use->getOpcode() == ISD::CopyToReg) in hasNoVMLxHazardUse()
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| D | ARMISelLowering.cpp | 2380 if (Copy->getOpcode() == ISD::CopyToReg) { in isUsedByReturnOnly()
2392 if (UI->getOpcode() != ISD::CopyToReg) in isUsedByReturnOnly()
2420 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0)) in isUsedByReturnOnly()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9703 if (Copy->getOpcode() == ISD::CopyToReg) { in isUsedByReturnOnly()
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