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/external/libhevc/common/arm/
Dihevc_sao_band_offset_chroma.s147 VLD1.8 D10,[r14]! @band_table_v.val[1]
207 …VADD.I8 D14,D10,D30 @band_table_v.val[1] = vadd_u8(band_table_v.val[1], band_p…
219 …VADD.I8 D10,D14,D28 @band_table_v.val[1] = vadd_u8(band_table_v.val[1], vdup_n…
250 VCLE.U8 D19,D10,D29 @vcle_u8(band_table.val[1], vdup_n_u8(16))
252 VORR.U8 D10,D10,D19 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
264 VAND.U8 D10,D10,D19 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
Dihevc_sao_edge_offset_class0_chroma.s104 VLD1.8 D10,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
203 VTBL.8 D14,{D10},D14 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
207 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
222 VTBL.8 D24,{D10},D24 @II vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
226 VTBL.8 D25,{D10},D25 @II vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
368 VTBL.8 D14,{D10},D14 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
372 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
387 VTBL.8 D28,{D10},D28 @II vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
391 VTBL.8 D29,{D10},D29 @II vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
Dihevc_sao_edge_offset_class0.s96 VLD1.8 D10,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
202 VTBL.8 D14,{D10},D14 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
206 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
217 VTBL.8 D28,{D10},D28 @II vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
220 VTBL.8 D29,{D10},D29 @II vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
312 VTBL.8 D24,{D10},D24 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
313 VTBL.8 D25,{D10},D25 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
Dihevc_sao_band_offset_luma.s161 VCLE.U8 D10,D2,D29 @vcle_u8(band_table.val[1], vdup_n_u8(16))
164 VORR.U8 D2,D2,D10 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
176 VAND.U8 D2,D2,D10 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
Dihevc_sao_edge_offset_class1.s127 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
178 …VMOVL.U8 Q10,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
237 …VMOVL.U8 Q13,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
271 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
315 …VMOVL.U8 Q10,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
355 …VMOVL.U8 Q13,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
Dihevc_sao_edge_offset_class1_chroma.s132 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
183 …VMOVL.U8 Q10,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
255 …VMOVL.U8 Q13,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
289 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
340 …VMOVL.U8 Q10,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
391 …VMOVL.U8 Q13,D10 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(v…
Dihevc_sao_edge_offset_class2.s236 …VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_u…
306 VTBL.8 D10,{D7},D18 @I offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
311 …VADDW.S8 Q10,Q10,D10 @I pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0…
408 … VTBL.8 D10,{D7},D18 @III offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
409 …VADDW.S8 Q10,Q10,D10 @III pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val…
481 VTBL.8 D10,{D7},D18 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
485 …VADDW.S8 Q10,Q10,D10 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0],…
548 …VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_u…
683 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy - 1)
Dihevc_sao_edge_offset_class3.s251 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)
323 VTBL.8 D10,{D7},D18 @I offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
326 …VADDW.S8 Q10,Q10,D10 @I pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0…
439 … VTBL.8 D10,{D7},D18 @III offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
445 …VADDW.S8 Q10,Q10,D10 @III pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val…
577 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)
716 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)
Dihevc_sao_edge_offset_class2_chroma.s334 …VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_u…
707 …VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_u…
855 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2)
Dihevc_sao_edge_offset_class3_chroma.s324 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
716 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
884 VLD1.8 D10,[r10]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
/external/llvm/test/MC/MachO/
Dx86_32-symbols.s35 D10: label
/external/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.h63 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, in getCalleeSavedSpillSlots()
DHexagonRegisterInfo.td107 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s209 VQSHRN.S32 D10,Q10,#13 @//D10 = (V-128)*C1>>13 4 16-BIT VALUES
340 VQSHRN.S32 D10,Q10,#13 @//D10 = (V-128)*C1>>13 4 16-BIT VALUES
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h64 case D11: case D10: case D9: case D8: in isARMArea3Register()
DARMRegisterInfo.td110 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
143 def Q5 : ARMReg< 5, "q5", [D10, D11]>;
DARMCallingConv.td99 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
/external/eigen/blas/testing/
Ddblat1.f164 E 4.D10, 2.D-2, 1.D-5, 10.D0,
166 G 2.D10, 4.D-2, 1.D-5, 10.D0,
193 DTRUE(1,6) = 4.D10 / (1.5D0 * D12 * D12)
201 DTRUE(2,8) = 2.D10 / (1.5D0 * D12 * D12)
/external/valgrind/memcheck/
Dmc_machine.c884 if (o >= GOF(D10) && o+sz <= GOF(D10)+SZB(D10)) return GOF(D10); in get_otrack_shadow_offset_wrk()
915 if (o >= GOF(D10) && o+sz <= GOF(D10)+2*SZB(D10)) return GOF(D10); // Q5 in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td200 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>;
232 def Q5 : Rq<20, "F20", [D10, D11]>;
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h122 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
162 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp118 case AArch64::D10: in isOdd()
DAArch64RegisterInfo.td330 def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
365 def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp417 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && in generateCompactUnwindEncoding()
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s899 @;Q5 -> D10:D11
909 @;D10 : sad_top
930 @;D10 : sad_top
1049 @D10 S2 S3 A2 A3

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