Searched refs:DEXT (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 88 if (Opcode == Mips::DEXT) in LowerDextDins()
105 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU); in LowerDextDins()
111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM); in LowerDextDins()
167 case Mips::DEXT: in encodeInstruction()
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 69 // DEXT: 0 < pos + size <= 63
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| D | Mips64InstrInfo.td | 277 // DEXT: 0 < pos + size <= 63
279 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>,
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| /external/clang/test/Parser/ |
| D | opencl-atomics-cl20.cl | 3 // RUN: %clang_cc1 %s -verify -fsyntax-only -cl-std=CL2.0 -DCL20 -DEXT
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 491 DEXT = ((0U << 3) + 3), enumerator
1230 case DEXT: in InstructionType()
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| D | disasm-mips64.cc | 1459 case DEXT: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2426 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT); in dext_()
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| D | simulator-mips64.cc | 3885 case DEXT: { // Mips64r2 instruction. in DecodeTypeRegisterSPECIAL3()
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| /external/valgrind/none/tests/mips64/ |
| D | extract_insert_bit_field.stdout.exp-mips64r2 | 387 --- DEXT ---
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