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Searched refs:DstRC (Results 1 – 25 of 25) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp143 const TargetRegisterClass *DstRC = in getCopyRegClasses() local
148 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
152 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
158 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
204 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
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DSILowerI1Copies.cpp107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); in runOnMachineFunction() local
110 if (DstRC == &AMDGPU::VReg_1RegClass && in runOnMachineFunction()
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) && in runOnMachineFunction()
DSIInstrInfo.cpp493 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const { in getMovOpcode()
495 if (DstRC->getSize() == 4) { in getMovOpcode()
496 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
497 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
499 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
2031 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0); in legalizeOperands() local
2032 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()
2064 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in legalizeOperands() local
2066 if (DstRC != Src0RC) { in legalizeOperands()
2068 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC); in legalizeOperands()
DSIInstrInfo.td1135 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1147 field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
1196 let Outs32 = (outs DstRC:$dst);
1197 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1211 let Outs32 = (outs DstRC:$dst);
1212 let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
1220 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1226 let DstRC = RegisterOperand<VGPR_32>;
1231 let DstRC = RegisterOperand<VReg_64>;
1291 (inst p.DstRC:$dst),
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DSIInstrInfo.h127 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
/external/llvm/utils/TableGen/
DFastISelEmitter.cpp193 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
275 if (DstRC) { in initialize()
276 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
279 DstRC = RC; in initialize()
481 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
489 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
490 if (!DstRC) in collectPatterns()
529 DstRC)) in collectPatterns()
580 DstRC, in collectPatterns()
/external/llvm/lib/Target/X86/
DX86InstrMMX.td185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
191 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
192 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>,
197 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
203 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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DX86InstrSSE.td1469 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1472 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1473 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1475 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1476 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1480 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1484 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1487 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1492 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1495 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
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DX86InstrInfo.cpp6270 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand() local
6275 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
6344 const TargetRegisterClass *DstRC = nullptr; in unfoldMemoryOperand() local
6346 DstRC = getRegClass(MCID, 0, &RI, MF); in unfoldMemoryOperand()
6347 VTs.push_back(*DstRC->vt_begin()); in unfoldMemoryOperand()
6380 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget), in unfoldMemoryOperand()
DX86InstrAVX512.td4871 RegisterClass DstRC, Intrinsic Int,
4874 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4876 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4877 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4881 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
161 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
164 DstRC = UseRC; in EmitCopyFromReg()
166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
175 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
333 const TargetRegisterClass *DstRC = nullptr; in AddRegisterOperand() local
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); in AddRegisterOperand()
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in AddRegisterOperand()
592 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
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/external/llvm/lib/Target/Mips/
DMipsInstrFPU.td121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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DMicroMips32r6InstrInfo.td571 class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
575 dag OutOperandList = (outs DstRC:$ft);
578 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
602 string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
605 dag OutOperandList = (outs DstRC:$ft);
608 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
702 class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
706 dag OutOperandList = (outs DstRC:$ft);
709 list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
DMipsMSAInstrInfo.td3559 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3561 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3616 RegisterClass DstRC, MSAInst Insn,
3620 DstRC),
3624 RegisterClass DstRC, MSAInst Insn,
3628 DstRC),
3632 RegisterClass DstRC> :
3633 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3636 RegisterClass DstRC> :
3637 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
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DMipsInstrInfo.td1141 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1142 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
1143 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
1152 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
1153 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
1154 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
DMipsDSPInstrInfo.td1307 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1310 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp132 const TargetRegisterClass *DstRC = in processBlock() local
142 unsigned NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
DPPCVSXSwapRemoval.cpp857 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
858 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables()
871 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
/external/llvm/lib/CodeGen/
DRegisterCoalescer.cpp343 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
380 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
959 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local
961 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1280 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
1285 std::swap(SrcRC, DstRC); in joinCopy()
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DPeepholeOptimizer.cpp429 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
430 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
431 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY()
537 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h184 const TargetRegisterClass *DstRC,
DARMBaseRegisterInfo.cpp758 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
769 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
777 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()
DARMFastISel.cpp2043 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); in FinishCall() local
2044 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
2063 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); in FinishCall() local
2065 unsigned ResultReg = createResultReg(DstRC); in FinishCall()
/external/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp641 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm() local
645 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC)) in isValidInsertForm()
648 if (DstRC != SrcRC) in isValidInsertForm()
650 if (DstRC == InsRC) in isValidInsertForm()
653 if (DstRC == &Hexagon::DoubleRegsRegClass) in isValidInsertForm()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h873 const TargetRegisterClass *DstRC, in shouldCoalesce() argument